View S3FK318_1303784.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

S3CK318/FK318
CalmRISC 8-Bit CMOS MICROCONTROLLER USER'S MANUAL Revision 1
Important Notice
The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product.
S3CK318/FK318 8-Bit CMOS Microcontroller User's Manual, Revision 1 Publication Number: 21-S3-CK318/FK318-042004 (c) 2004 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics.
Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BVQ1 Certificate No. 9330). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. Samsung Electronics Co., Ltd. San #24 Nongseo-Lee, Kiheung-Eup Yongin-City Kyungi-Do, Korea C.P.O. Box #37, Suwon 449-900 TEL: (82)-(331)-209-1907 FAX: (82)-(331)-209-1889 Home-Page URL: Http://www.samsungsemi.com/ Printed in the Republic of Korea
Preface
The S3CK318/FK318 Microcontroller User's Manual is designed for application designers and programmers who are using the S3CK318/FK318 microcontroller for application development. It is organized in two main parts: Part I Programming Model Part II Hardware Descriptions
Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has seven chapters: Chapter 1 Chapter 2 Chapter 3 Chapter 4 Product Overview Address Spaces Register Memory Map Chapter 5 Chapter 6 Chapter 7 Hardware Stack Exceptions Instruction Set
Chapter 1, "Product Overview," is a high-level introduction to S3CK318/FK318 with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types. Chapter 2, "Address Spaces," describes program and data memory spaces. Chapter 2 also describes ROM code option. Chapter 3, "Register," describes the special registers. Chapter 4, "Memory Map," describes the internal register file. Chapter 5, "Hardware Stack," describes the S3CK318/FK318 hardware stack structure in detail. Chapter 6, "Exception," describes the S3CK318/FK318 exception structure in detail. A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in Part II. If you are not yet familiar with the S3CK-series microcontroller family and are reading this manual for the first time, we recommend that you first read Chapters 1-3 carefully. Then, briefly look over the detailed information in Chapters 4, 5, 6 and 7. Later, you can reference the information in Part I as necessary. Part II "hardware Descriptions," has detailed information about specific hardware components of the S3CK318/FK318 microcontroller. Also included in Part II are electrical, mechanical. It has 17 chapters: Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Clock Circuit RESET and Power-Down I/O Ports Basic Timer/Watchdog Timer Watch Timer 16-bit Timer 0 8-bit Timer 1 Serial I/O Interface Battery Level Detector Chapter 17 Chapter 18 Chapter 19 Chapter 20 Chapter 21 Chapter 22 Chapter 23 Chapter 24 LCD Controller/Driver 10-Bit Analog-to-Digital Converter D/A Converter Frequency Counter Electrical Data Mechanical Data S3FK318 Flash MCU Development Tools
One order form is included at the back of this manual to facilitate customer order for S3CK318/FK318 microcontrollers: the Flash Factory Writing Order Form. You can photocopy this form, fill it out, and then forward it to your local Samsung Sales Representative.
S3CK318/FK318 MICROCONTROLLER
iii
Table of Contents
Part I -- Programming Model
Chapter 1 Product Overview
Overview ............................................................................................................................................. 1-1 Features ............................................................................................................................................. 1-5 Block Diagram .................................................................................................................................... 1-7 Pin Assignment................................................................................................................................... 1-8 Pin Descriptions .................................................................................................................................. 1-9 Pin Circuits......................................................................................................................................... 1-11
Chapter 2
Address Spaces
Overview ............................................................................................................................................. 2-1 Program Memory (ROM) ...................................................................................................................... 2-1 ROM Code Option (RCOD_OPT)........................................................................................................... 2-4 Data Memory Organization................................................................................................................... 2-6
Chapter 3
Register
Overview ............................................................................................................................................. 3-1 Index Registers: IDH, IDL0 and IDL1.............................................................................................. 3-2 Link Registers: ILX, ILH and ILL .................................................................................................... 3-2 Status Register 0: SR0 ................................................................................................................ 3-3 Status Register 1: SR1 ................................................................................................................ 3-4
Chapter 4
Memory Map
Overview ............................................................................................................................................. 4-1
S3CK318/FK318 MICROCONTROLLER
v
Table of Contents (Continued)
Chapter 5 Hardware Stack
Overview ............................................................................................................................................. 5-1
Chapter 6
Exceptions
Overview ............................................................................................................................................. 6-1 Hardware Reset........................................................................................................................... 6-1 IRQ[0] Exception......................................................................................................................... 6-2 IRQ[1] Exception (Level-Sensitive)................................................................................................. 6-2 Hardware Stack Full Exception..................................................................................................... 6-2 Break Exception.......................................................................................................................... 6-2 Exceptions (or Interrupts)............................................................................................................. 6-3 Interrupt Mask Registers .............................................................................................................. 6-5 Interrupt Priority Register.............................................................................................................. 6-6
Chapter 7
Instruction Set
Overview ............................................................................................................................................. 7-1 Glossary..................................................................................................................................... 7-1 Instruction Set Map ............................................................................................................................. 7-2 Quick Reference.................................................................................................................................. 7-9 Instruction Group Summary .................................................................................................................. 7-12 ALU Instructions.......................................................................................................................... 7-12 Shift/Rotate Instructions ............................................................................................................... 7-16 Load Instructions ......................................................................................................................... 7-18 Branch Instructions...................................................................................................................... 7-21 Bit Manipulation Instructions......................................................................................................... 7-25 Miscellaneous Instruction............................................................................................................. 7-26 Pseudo Instructions ..................................................................................................................... 7-29
vi
S3CK318/FK318 MICROCONTROLLER
Table of Contents (Continued)
Part II -- Hardware Descriptions
Chapter 8 Clock Circuit
System Clock Circuit........................................................................................................................... 8-1
Chapter 9
RESET and Power-Down
Overview ............................................................................................................................................. 9-1
Chapter 10
Port Port Port Port Port Port Port
I/O Ports
0................................................................................................................................................. 10-1 1................................................................................................................................................. 10-2 2................................................................................................................................................. 10-4 3................................................................................................................................................. 10-5 4................................................................................................................................................. 10-7 5................................................................................................................................................. 10-8 6................................................................................................................................................. 10-9
Chapter 11
Basic Timer/Watchdog Timer
Overview ............................................................................................................................................. 11-1 Block Diagram ............................................................................................................................ 11-2
Chapter 12
Watch Timer
Overview ............................................................................................................................................. 12-1 Watch Timer Circuit Diagram........................................................................................................ 12-2
Chapter 13
16-Bit Timer 0
Overview ............................................................................................................................................. 13-1 Function Description............................................................................................................................ 13-2 Timer 0 Control Register (T0CON) ......................................................................................................... 13-3 Block Diagram .................................................................................................................................... 13-4
S3CK318/FK318 MICROCONTROLLER
vii
Table of Contents (Continued)
Chapter 14 8-Bit Timer 1
Overview ............................................................................................................................................. 14-1 Function Description............................................................................................................................ 14-1 Timer 1 Control Register (T1CON) ................................................................................................. 14-2 Block Diagram ............................................................................................................................ 14-3
Chapter 15
Serial I/O Interface
Overview ............................................................................................................................................. 15-1 Programming Procedure............................................................................................................... 15-1 SIO Control Register (SIOCON) ............................................................................................................ 15-2 SIO Pre-Scaler Register (SIOPS).......................................................................................................... 15-2 Block Diagram .................................................................................................................................... 15-3 Serial I/O Timing Diagram..................................................................................................................... 15-4
Chapter 16
Battery Level Detector
Overview ............................................................................................................................................. 16-1 Battery Level Detector Control Register (BLDCON) ......................................................................... 16-2
Chapter 17
LCD Controller/Driver
Overview ............................................................................................................................................. 17-1 LCD Circuit Diagram .................................................................................................................... 17-2 LCD RAM Address Area .............................................................................................................. 17-3 LCD Mode Control Register (LMOD).............................................................................................. 17-4 LCD Port Control Registers (LPOT0, LPOT1, LPOT2) ..................................................................... 17-5 LCD Voltage Dividing Resistors..................................................................................................... 17-7 Common (COM) Signals .............................................................................................................. 17-8 Segment (SEG) Signals............................................................................................................... 17-8
Chapter 18
10-Bit Analog-to-Digital Converter
Overview ............................................................................................................................................. 18-1 Function Description............................................................................................................................ 18-1 Conversion Timing ....................................................................................................................... 18-2 A/D Converter Control Register (ADCON)....................................................................................... 18-2 Internal Reference Voltage Levels.................................................................................................. 18-3 Block Diagram .................................................................................................................................... 18-3
viii
S3CK318/FK318 MICROCONTROLLER
Table of Contents (Continued)
Chapter 19 D/A Converter
Overview ............................................................................................................................................. 19-1 Function Description.................................................................................................................... 19-1 D/A Converter Data Register (DADATAH/DADATAL)....................................................................... 19-3
Chapter 20
Frequency Counter
Overview ............................................................................................................................................. 20-1 FC Contorl Register (FCCON)............................................................................................................... 20-2 Input Pin Configuration for an AC Frequency Count ......................................................................... 20-3 FC Mode Register (FCMOD)................................................................................................................. 20-4 Gate Times ......................................................................................................................................... 20-5 Frequency Counter (FC) Operation........................................................................................................ 20-8 FC Data Calculation............................................................................................................................. 20-9
Chapter 21 Chapter 22
Electrical Data Mechanical Data
Overview ............................................................................................................................................. 22-1
Chapter 23
S3FK318 Flash MCU
Overview ............................................................................................................................................. 23-1
S3CK318/FK318 MICROCONTROLLER
ix
Table of Contents (Continued)
Chapter 24 Development Tools
Overview ............................................................................................................................................. 24-1 CALMSHINE: IDE (Integrated Development Environment)................................................................ 24-1 Invisible Mds: In-Circuit Emulator .................................................................................................. 24-1 CALMRISC8 C-Compiler: CALM8CC ............................................................................................. 24-1 CALMRISC8 Relocatable Assembler: CALM8ASM......................................................................... 24-1 CALMRISC8 Linker: CALM8LINK .................................................................................................. 24-1 Emulation Probe Board Configuration .................................................................................................... 24-2 External Event Input Headers........................................................................................................ 24-3 Event Match Output Headers ........................................................................................................ 24-3 External Break Input Headers (U6) ................................................................................................ 24-3 Power Selection .......................................................................................................................... 24-4 Clock Selection........................................................................................................................... 24-4 Use Clock Setting for External Clock Mode.................................................................................... 24-5 Sub Clock Setting ....................................................................................................................... 24-5 JP1 Pin Assignment .................................................................................................................... 24-6
x
S3CK318/FK318 MICROCONTROLLER
List of Figures
Figure Number 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 2-1 2-2 2-3 2-4 2-5 2-6 3-1 4-1 5-1 5-2 5-3 5-4 5-5 6-1 6-2 6-3 6-4 Title Page Number
Top Block Diagram.......................................................................................................... 1-2 CalmRISC Pipeline Diagram............................................................................................. 1-3 CalmRISC Pipeline Stream Diagram ................................................................................. 1-4 Block Diagram................................................................................................................ 1-7 Pin Assignment (44-QFP-1010B)...................................................................................... 1-8 Pin Circuit Type B (nRESET) ........................................................................................... 1-11 Pin Circuit Type B-4 (P0) ................................................................................................. 1-11 Pin Circuit Type E-4 (P1, P3.1) ........................................................................................ 1-11 Pin Circuit Type E-5 (P3.0) .............................................................................................. 1-11 Pin Circuit Type F-16A (P2) ............................................................................................ 1-12 Pin Circuit Type H-23 ...................................................................................................... 1-12 Pin Circuit Type H-32 (P4, P5, and P6) ............................................................................. 1-13 Pin Circuit Type H-32A (P3.2-P3.5).................................................................................. 1-13 Program Memory Organization......................................................................................... 2-1 Relative Jump Around Page Boundary............................................................................... 2-2 Program Memory Layout ................................................................................................. 2-3 ROM Code Option (RCOD_OPT) ...................................................................................... 2-5 Data Memory Map of CalmRISC8 ..................................................................................... 2-6 Data Memory Map of S3CK318 ........................................................................................ 2-7 Bank Selection by Setting of GRB Bits and IDB Bit............................................................ 3-3 Memory Map Area .......................................................................................................... 4-1 Hardware Stack .............................................................................................................. 5-1 Even and Odd Bank Selection Example ............................................................................ 5-2 Stack Operation with PC [19:0] ........................................................................................ 5-3 Stack Operation with Registers ........................................................................................ 5-4 Stack Overflow................................................................................................................ 5-5 Interrupt Structure ........................................................................................................... 6-3 Interrupt Block Diagram ................................................................................................... 6-4 Interrupt Mask Register ................................................................................................... 6-5 Interrupt Priority Register ................................................................................................. 6-6
S3CK318/FK318 MICROCONTROLLER
xi
List of Figures (Continued)
Figure Number 8-1 8-2 8-3 8-4 8-5 8-6 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 11-1 11-2 12-1 13-1 13-2 13-3 14-1 14-2 14-3 14-4 15-1 15-2 15-3 15-4 15-5 Title Page Number
Main Oscillator Circuit (Crystal or Ceramic Oscillator) ........................................................ 8-1 Main Oscillator Circuit (RC Oscillator)............................................................................... 8-1 Sub Oscillator Circuit (Crystal or Ceramic Oscillator).......................................................... 8-2 System Clock Circuit Diagram ......................................................................................... 8-3 Power Control Register (PCON)........................................................................................ 8-4 Oscillator Control Register (OSCCON) .............................................................................. 8-4 Port 0 Pull-up Control Register (P0PUR) ........................................................................... 10-1 Port 1 Control Register (P1CON) ...................................................................................... 10-2 Port 1 Pull-up Control Register (P1PUR) ........................................................................... 10-2 Port 1 Interrupt Edge Selection Register (P1EDGE) ........................................................... 10-3 Port 2 Control Register (P2CON) ...................................................................................... 10-4 Port 2 Pull-up Control Register (P2PUR) ........................................................................... 10-4 Port 3 Control Register A (P3CONA)................................................................................. 10-5 Port 3 Control Register B (P3CONB)................................................................................. 10-5 Port 3 Control Register C (P3CONC)................................................................................. 10-6 Port 4 High-Byte Control Register (P4CONH)..................................................................... 10-7 Port 4 Low-Byte Control Register (P4CONL)...................................................................... 10-7 Port 5 High-Byte Control Register (P5CONH)..................................................................... 10-8 Port 5 Low-Byte Control Register (P5CONL)...................................................................... 10-8 Port 6 Control Register (P6CON) ...................................................................................... 10-9 Watchdog Timer Control Register (WDTCON).................................................................... 11-1 Basic Timer & Watchdog Timer Functional Block Diagram.................................................. 11-2 Watch Timer Circuit Diagram ........................................................................................... 12-2 Timer 0 Control Register (T0CON)..................................................................................... 13-3 Timer 0 Functional Block Diagram .................................................................................... 13-4 Timer 0 Counter and Data Registers (T0CNTH/L, T0DATAH/L)............................................. 13-5 Timer 1 Control (T1CON).................................................................................................. 14-2 Timer 1 Functional Block Diagram .................................................................................... 14-3 Timer 1 Counter Register (T1CNT) .................................................................................... 14-4 Timer 1 Data Register (T1DATA)....................................................................................... 14-4 Serial I/O Module Control Registers (SIOCON)................................................................... 15-2 SIO Pre-scaler Register (SIOPS)...................................................................................... 15-2 SIO Function Block Diagram............................................................................................ 15-3 Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0) ............................ 15-4 Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)............................. 15-4
xii
S3CK318/FK318 MICROCONTROLLER
List of Figures (Continued)
Figure Number 16-1 16-2 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 18-1 18-2 18-3 18-4 19-1 19-2 19-3 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9 Title Page Number
Block Diagram for Battery Level Detect ............................................................................. 16-1 Battery Level Detector Circuit and Control Register ............................................................ 16-2 LCD Function Diagram .................................................................................................... 17-1 LCD Circuit Diagram........................................................................................................ 17-2 LCD Display Data RAM Organization................................................................................ 17-3 LCD Mode Control Register (LMOD) ................................................................................. 17-4 LCD Port Control Register 0 (LPOT0)................................................................................ 17-5 LCD Port Control Register 1 (LPOT1)................................................................................ 17-5 LCD Port Control Register 2 (LPOT2)................................................................................ 17-6 LCD Bias Circuit Connection............................................................................................ 17-7 LCD Signal Waveforms (1/3 Duty, 1/3 Bias)....................................................................... 17-9 LCD Signal Waveforms (1/4 Duty, 1/3 Bias)....................................................................... 17-10 LCD Signal Waveforms (1/8 Duty, 1/4 Bias)....................................................................... 17-11 LCD Signal Waveforms (1/8 Duty, 1/5 Bias)....................................................................... 17-13 A/D Converter Control Register (ADCON) .......................................................................... 18-2 A/D Converter Data Register (ADDATAH/ADDATAL) .......................................................... 18-3 A/D Converter Functional Block Diagram........................................................................... 18-3 Recommended A/D Converter Circuit for Highest Absolute Accuracy ................................... 18-4 DAC Circuit Diagram ....................................................................................................... 19-2 Digital to Analog Converter Control Register (DACON) ........................................................ 19-2 D/A Converter Data Register (DADATAH/DADATAL) .......................................................... 19-3 Frequency Counter Block Diagram ................................................................................... 20-1 Frequency Counter Control Register (FCCON) ................................................................... 20-2 Frequency Counter Register (FCNT2-FCNT0).................................................................... 20-2 FMF and AMF Pin Configuration....................................................................................... 20-3 Frequency Counter Mode Register (FCMOD)..................................................................... 20-4 Gate Timing (16, 32, or 64-ms)......................................................................................... 20-5 Gate Timing (When Open) ............................................................................................... 20-6 Gate Timing (16-ms Error)................................................................................................ 20-7 Input Timing for External Interrupts (P1, P3.0-P3.2) ........................................................... 21-4 Input Timing for RESET ................................................................................................... 21-4 Stop Mode Release Timing When Initiated by a RESET ..................................................... 21-5 Stop Mode (Main) Release Timing Initiated by Interrupts..................................................... 21-6 Stop Mode (Sub) Release Timing Initiated by Interrupts ...................................................... 21-6 Serial Data Transfer Timing .............................................................................................. 21-10 Clock Timing Measurement at XIN..................................................................................... 21-12 Clock Timing Measurement at XT IN ................................................................................... 21-12 Operating Voltage Range................................................................................................. 21-13
S3CK318/FK318 MICROCONTROLLER
xiii
List of Figures (Continued)
Figure Number 22-1 23-1 24-1 Title Page Number
44-Pin QFP Package Dimensions (44-QFP-1010B)............................................................ 22-1 S3FK318 Pin Assignments (44-QFP-1010B) ..................................................................... 23-2 Emulation Probe Board Configuration................................................................................ 24-2
xiv
S3CK318/FK318 MICROCONTROLLER
List of Tables
Table Number 1-1 3-1 3-2 3-3 4-1 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 12-1 16-1 19-1 20-1 20-2 20-3 Title Page Number
Pin Descriptions ............................................................................................................. 1-9 General and Special Purpose Registers ............................................................................ 3-1 Status Register 0 configuration......................................................................................... 3-3 Status Register 1: SR1.................................................................................................... 3-4 Registers ....................................................................................................................... 4-2 Exceptions ..................................................................................................................... 6-1 Instruction Notation Conventions....................................................................................... 7-1 Overall Instruction Set Map .............................................................................................. 7-2 Instruction Encoding........................................................................................................ 7-4 Index Code Information ("idx") .......................................................................................... 7-7 Index Modification Code Information ("mod")...................................................................... 7-7 Condition Code Information ("cc") ..................................................................................... 7-7 "ALUop1" Code Information.............................................................................................. 7-8 "ALUop2" Code Information.............................................................................................. 7-8 "MODop1" Code Information............................................................................................. 7-8 Watch Timer Control Register (WTCON): 8-Bit R/W ........................................................... 12-1 BLDCON Value and Detection Level ................................................................................. 16-2 DADATA Setting to Generate Analog Voltage.................................................................... 19-3 Frequency Counter Control Register (FCCON) Bit Settings in Normal Operating Mode .......... 20-3 Frequency Counter Control Register (FCCON) Bit Settings in Power-Down Mode.................. 20-3 FC Frequency Characteristics.......................................................................................... 20-9
S3CK318/FK318 MICROCONTROLLER
xv
List of Tables (Continued)
Table Number 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 21-11 21-12 21-13 21-14 21-15 23-1 Title Page Number
Absolute Maximum Ratings ............................................................................................. 21-1 D.C. Electrical Characteristics ......................................................................................... 21-1 A.C. Electrical Characteristics ......................................................................................... 21-4 Input/Output Capacitance ................................................................................................ 21-5 Data Retention Supply Voltage in Stop Mode .................................................................... 21-5 A/D Converter Electrical Characteristics............................................................................ 21-7 D/A Converter Electrical Characteristics............................................................................ 21-7 Characteristics of Frequency Counter ............................................................................... 21-8 Characteristics of Battery Level Detect Circuit ................................................................... 21-8 LCD Contrast Level Characteristics................................................................................... 21-9 Synchronous SIO Electrical Characteristics ...................................................................... 21-10 Main Oscillator Frequency (fOSC1) .................................................................................... 21-11 Main Oscillator Clock Stabilization Time (TST1).................................................................. 21-11 Sub Oscillator Frequency (fOSC2)...................................................................................... 21-12 Sub Oscillator (Crystal) Start up Time (t ST2) ...................................................................... 21-13 Descriptions of Pins Used to Read/Write the FLASH ROM ................................................. 23-3
xvi
S3CK318/FK318 MICROCONTROLLER
List of Programming Tips
Description Page Number
Chapter 6: Exceptions Interrupt Programming Tip 1.................................................................................................................. 6-7 Interrupt Programming Tip 2.................................................................................................................. 6-8
S3CK318/FK318 MICROCONTROLLER
xvii
List of Instruction Descriptions
Instruction Mnemonic ADC ADD AND AND SR0 BANK BITC BITR BITS BITT BMC/BMS CALL CALLS CLD CLD COM COM2 COMC COP CP CPC DEC DECC DI EI IDLE INC INCC IRET JNZD JP JR LCALL LD adr:8 Full Instruction Name Page Number
Add with Carry .................................................................................................... 7-30 Add ................................................................................................................... 7-31 Bit-wise AND...................................................................................................... 7-32 Bit-wise AND with SR0........................................................................................ 7-33 GPR Bank Selection ........................................................................................... 7-34 Bit Complement .................................................................................................. 7-35 Bit Reset............................................................................................................ 7-36 Bit Set ............................................................................................................... 7-37 Bit Test.............................................................................................................. 7-38 TF bit clear/set ................................................................................................... 7-39 Conditional subroutine call (Pseudo Instruction) .................................................... 7-40 Call Subroutine ................................................................................................... 7-41 Load into Coprocessor......................................................................................... 7-42 Load from Coprocessor........................................................................................ 7-43 1's or Bit-wise Complement.................................................................................. 7-44 2's Complement .................................................................................................. 7-45 Bit-wise Complement with Carry ........................................................................... 7-46 Coprocessor....................................................................................................... 7-47 Compare ............................................................................................................ 7-48 Compare with Carry............................................................................................. 7-49 Decrement ......................................................................................................... 7-50 Decrement with Carry .......................................................................................... 7-51 Disable Interrupt (Pseudo Instruction).................................................................... 7-52 Enable Interrupt (Pseudo Instruction) ................................................................... 7-53 Idle Operation (Pseudo Instruction) ...................................................................... 7-54 Increment ........................................................................................................... 7-55 Increment with Carry ........................................................................................... 7-56 Return from Interrupt Handling .............................................................................. 7-57 Jump Not Zero with Delay Slot ............................................................................. 7-58 Conditional Jump (Pseudo Instruction) ................................................................. 7-59 Conditional Jump Relative .................................................................................... 7-60 Conditional Subroutine Call .................................................................................. 7-61 Load into Memory ............................................................................................... 7-62
S3CK318/FK318 MICROCONTROLLER
xix
List of Instruction Descriptions (Continued)
Instruction Mnemonic LD @idm LD LD LD LD LD SPR LD SPR0 LDC LJP LLNK LNK LNKS LRET NOP OR OR SR0 POP POP PUSH RET RL RLC RR RRC SBC SL SLA SR SRA STOP SUB SWAP SYS TM XOR Full Instruction Name Page Number
Load into Memory Indexed................................................................................... 7-63 Load Register ..................................................................................................... 7-64 Load GPR:bankd, GPR:banks.............................................................................. 7-65 Load GPR, TBH/TBL........................................................................................... 7-66 Load TBH/TBL, GPR........................................................................................... 7-67 Load SPR .......................................................................................................... 7-68 Load SPR0 Immediate......................................................................................... 7-69 Load Code.......................................................................................................... 7-70 Conditional Jump ................................................................................................ 7-71 Linked Subroutine Call Conditional........................................................................ 7-72 Linked Subroutine Call (Pseudo Instruction) .......................................................... 7-73 Linked Subroutine Call......................................................................................... 7-74 Return from Linked Subroutine Call....................................................................... 7-75 No Operation ...................................................................................................... 7-76 Bit-wise OR........................................................................................................ 7-77 Bit-wise OR with SR0.......................................................................................... 7-78 POP .................................................................................................................. 7-79 POP to Register ................................................................................................. 7-80 Push Register..................................................................................................... 7-81 Return from Subroutine........................................................................................ 7-82 Rotate Left ......................................................................................................... 7-83 Rotate Left with Carry .......................................................................................... 7-84 Rotate Right ....................................................................................................... 7-85 Rotate Right with Carry........................................................................................ 7-86 Subtract with Carry ............................................................................................. 7-87 Shift Left ............................................................................................................ 7-88 Shift Left Arithmetic............................................................................................. 7-89 Shift Right .......................................................................................................... 7-90 Shift Right Arithmetic .......................................................................................... 7-91 Stop Operation (Pseudo Instruction) .................................................................... 7-92 Subtract............................................................................................................. 7-93 Swap ................................................................................................................. 7-94 System.............................................................................................................. 7-95 Test Multiple Bits................................................................................................ 7-96 Exclusive OR...................................................................................................... 7-97
xx
S3CK318/FK318 MICROCONTROLLER
NOTIFICATION OF REVISIONS
ORIGINATOR: PRODUCT NAME: DOCUMENT NAME: DOCUMENT NUMBER: EFFECTIVE DATE: SUMMARY:
April, 2004 Samsung Electronics, LSI Development Group, Ki-Heung, South Korea
S3CK318/FK318 8-bit CMOS Microcontroller
S3CK318/FK318 User's Manual, Revision 1
21-S3-CK318/FK318-042004
As a result of additional product testing and evaluation, some specifications published in the S3CK318/FK318 User's Manual, Revision 0, have been changed. These changes for S3CK318/FK318 microcontroller, which are described in detail in the Revision Descriptions section below, are related to the followings: -- Chapter 21. Electrical Data
DIRECTIONS:
Please note the changes in your copy (copies) of the S3CK318/FK318 User's Manual, Revision 0. Or, simply attach the Revision Descriptions of the next page to S3CK318/FK318 User's Manual, Revision 0.
REVISION HISTORY
Revision 0 1 Date November, 2003 April, 2004 Remark Preliminary Spec for internal release only. First edition. Reviewed by Finechips. Second edition. Reviewed by Finechips.
REVISION DESCRIPTIONS
1. OPERATING VOLTAGE (PAGE 21-1)
The Operating voltage at 8MHz X-tal is changed 2.4V to 2.3V. The Operating voltage at 2MHz X-tal is changed 2.0V to 1.95V.
Table 21-2. D.C. Electrical Characteristics (TA = - 25 C to + 85 C, VDD = 1.95 V to 3.6 V) Parameter Operating voltage Symbol VDD fx = 8 MHz fx = 2 MHz Conditions Min 2.3 1.95 Typ - - Max 3.6 3.6 Unit V
2. CHARACTERISTICS OF BATTERY LEVEL DETECT CIRCUIT (PAGE 21-8)
Table 21-9. Characteristics of Battery Level Detect Circuit (TA = 25 C) Parameter Operating voltage of BLD Voltage of BLD Symbol VDDBLD VBLD BLDCON.4-.2 = 100b BLDCON.4-.2 = 101b BLDCON.4-.2 = 110b Conditions Min 1.95 1.95 2.15 2.3 Typ - 2.2 2.4 2.6 Max 3.6 2.45 2.65 2.9 Unit V
S3CK318/FK318
PRODUCT OVERVIEW
1
OVERVIEW
PRODUCT OVERVIEW
The S3CK318/FK318 single-chip CMOS microcontroller is designed for high performance using Samsung's new 8-bit CPU core, CalmRISC. CalmRISC is an 8-bit low power RISC microcontroller. Its basic architecture follows Harvard style, that is, it has separate program memory and data memory. Both instruction and data can be fetched simultaneously without causing a stall, using separate paths for memory access. Represented below is the top block diagram of the CalmRISC microcontroller.
1-1
PRODUCT OVERVIEW
S3CK318/FK318
20 PA[19:0] PD[15:0] Program Memory Address Generation Unit PC[19:0] 20 8 8 HS[0] Hardware Stack TBH DO[7:0] TBL HS[15] ABUS[7:0] BBUS[7:0] DI[7:0] ALUL ALUR R0 R1 R2 ALU Flag R3 GPR
RBUS
SR1 ILX Data Memory Address Generation Unit ILH
SR0 ILL IDL0
DA[15:0]
IDH IDL1 SPR
Figure 1-1. Top Block Diagram
1-2
S3CK318/FK318
PRODUCT OVERVIEW
The CalmRISC building blocks consist of: -- An 8-bit ALU -- 16 general purpose registers (GPR) -- 11 special purpose registers (SPR) -- 16-level hardware stack -- Program memory address generation unit -- Data memory address generation unit Sixteen GPRs are grouped into four banks (Bank0 to Bank3), and each bank has four 8-bit registers (R0, R1, R2, and R3). SPRs, designed for special purposes, include status registers, link registers for branch-link instructions, and data memory index registers. The data memory address generation unit provides the data memory address (denoted as DA[15:0] in the top block diagram) for a data memory access instruction. Data memory contents are accessed through DI[7:0] for read operations and DO[7:0] for write operations. The program memory address generation unit contains a program counter, PC[19:0], and supplies the program memory address through PA[19:0] and fetches the corresponding instruction through PD[15:0] as the result of the program memory access. CalmRISC has a 16-level hardware stack for low power stack operations as well as a temporary storage area.
Instruction Fetch (IF)
Instruction Decode/ Data Memory Access (ID/MEM)
Execution/Writeback (EXE/WB)
Figure 1-2. CalmRISC Pipeline Diagram CalmRISC has a 3-stage pipeline as described below: As can be seen in the pipeline scheme, CalmRISC adopts a register-memory instruction set. In other words, data memory where R is a GPR can be one operand of an ALU instruction as shown below: The first stage (or cycle) is the Instruction fetch stage (IF for short), where the instruction pointed by the program counter, PC[19:0] , is read into the Instruction Register (IR for short). The second stage is the Instruction Decode and Data Memory Access stage (ID/MEM for short), where the fetched instruction (stored in IR) is decoded and data memory access is performed, if necessary. The final stage is the Execute and Write-back stage (EXE/WB), where the required ALU operation is executed and the result is written back into the destination registers. Since CalmRISC instructions are pipelined, the next instruction fetch is not postponed until the current instruction is completely finished but is performed immediately after completing the current instruction fetch. The pipeline stream of instructions is illustrated in the following diagram.
1-3
PRODUCT OVERVIEW
S3CK318/FK318
/1
IF /2
ID/MEM IF /3
EXE/WB ID/MEM IF /4 EXE/WB ID/MEM IF EXE/WB IF /5 ID/MEM IF /6 EXE/WB ID/MEM IF EXE/WB ID/MEM EXE/WB
Figure 1-3. CalmRISC Pipeline Stream Diagram Most CalmRISC instructions are 1-word instructions, while same branch instructions such as long "call" and "jp" instructions are 2-word instructions. In Figure 1-3, the instruction, I4, is a long branch instruction, and it takes two clock cycles to fetch the instruction. As indicated in the pipeline stream, the number of clocks per instruction (CPI) is 1 except for long branches, which take 2 clock cycles per instruction.
1-4
S3CK318/FK318
PRODUCT OVERVIEW
FEATURES
CPU
*
24-bit Frequency Counter (FC)
* * * * *
CalmRISC core (8-bit RISC architecture)
Level = 300 mVpp (Min.) AMF input range = 0.5 to 5 MHz or 5 to 30 MHz FMF input range = 30 to 130 MHz Operating voltage: 2.0 V to 3.6 V Counter measurement function (16/32/64 msec)
Memory
* *
ROM: 4K-word (8K-byte) RAM: 256-byte (excluding LCD data RAM)
Stack
*
Size: maximum 16 word-level
Battery Level Detector
*
36 I/O Pins
* * *
Programmable detection voltage (2.2 V, 2.4V, 2.6 V)
Input only: 2 pins I/O: 10 pins 24 I/O pins are share with COM/SEG pins
8-Bit Serial I/O Interface
* * * *
8-bit transmit/receive mode 8-bit receive mode LSB-first/MSB-first transmission selectable Internal/external clock source
Basic Timer
* *
Overflow signal makes a system reset Watchdog function
A/D Converter
* * * *
16-bit Timer/Counter 0
* * *
Four analog input channels 25 s conversion speed at 8 MHz 10-bit conversion resolution Operating voltage: 2.0 V to 3.6 V
Programmable 16-bit timer Interval, capture, PWM mode Match/capture, overflow interrupt
8-bit Timer/Counter 1
* *
D/A Converter
* * *
Programmable 8-bit timer Match interrupt generator
One analog output channel 9-bit conversion resolution (R-2R) Operating voltage: 2.0 V to 3.6 V
Watch Timer
* * *
Real-time and interval time measurement Clock generation for LCD Four frequency outputs for buzzer sound (0.47/0.94/1.87/3.75 kHz at 75 kHz)
Oscillation Sources
* * * * *
Crystal, ceramic, RC for main clock Crystal for sub clock Main clock frequency: 0.4 - 8 MHz Sub clock frequency: 32.8 - 100 kHz CPU clock divider circuit (divided by 1, 2, 4, 8, 16, 32, 64, or 128)
LCD Controller/Driver
* * * *
Up to 20 segment pins 3, 4, and 8 common selectable Internal resistor circuit for LCD bias LCD Contrast Control
Two Power-Down Modes
* *
Idle (only CPU clock stops) Stop (System clock stops)
1-5
PRODUCT OVERVIEW
S3CK318/FK318
Interrupts
*
Operating Voltage Range
* *
2 Vectors, 14 interrupts
1.95 V to 3.6 V at 2 MHz (2MIPS) 2.3 V to 3.6 V at 8 MHz (8MIPS)
Instruction Execution Times
* *
125 ns at 8 MHz (main clock) 13.3 s at 75 kHz (sub clock)
Package Type
*
44-QFP-1010B
Operating Temperature Range
*
- 25 C to 85 C
1-6
S3CK318/FK318
PRODUCT OVERVIEW
BLOCK DIAGRAM
nRESET T0OUT/T0PWM/INT0/P1.0 T0CLK/INT1/P1.1 T0CAP/INT2/P1.2 16-Bit Timer/ Counter 0 8-Bit Timer/ Counter 1 AMF/P0.0 FMF/P0.1 INT0/T0OUT/T0PWM/P1.0 INT1//T0CLK/P1.1 INT2/T0CAP/P1.2 INT3/BUZ/P1.3 AD0-AD3/P2.0-P2.3 DAO/INT4/P3.0 INT5/P3.1 SEG0/INT6/P3.2 SEG1/SI/P3.3 SEG2/SO/P3.4 SEG3/SCK/P3.5 SEG4-SEG11 /P4.0-P4.7
XIN, XTIN XOUT, XTOUT BUZ/INT3/P1.3 COM0-COM3/P6.3-P6.0 LCD Driver COM4-COM7/SEG19-SEG16/ P5.7-P5.4 SEG0-SEG3/P3.2-P3.5/ INT6, SI, SO, SCK SEG4-SEG15/P4.0-P5.3
OSC, nRESET
Basic Timer
Watch Timer
Input Port 0 Serial I/O Port I/O Port 1 I/O Port and Interrupt Control Frequency Counter 10-bit A/D Converter Calm8 RISC CPU 9-bit D/A Converter 256-Byte Register File I/O Port 4 I/O Port 6 8K-Byte ROM I/O Port 5
SI/SEG1/P3.3 SO/SEG2/P3.4 SCK/SEG3/P3.5 AMF/P0.0 FMF/P0.1 AD0-AD3/P2.0-P2.3
I/O Port 2
DAO/P3.0/INT4 P5.0-P5.3/SEG12-SEG15 P5.4-P5.7/SEG16-SEG19 /COM7-COM4 P6.0-P6.3/COM3-COM0
I/O Port 3
Figure 1-4. Block Diagram
1-7
PRODUCT OVERVIEW
S3CK318/FK318
PIN ASSIGNMENT
P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 VDD VSS XOUT XIN TEST XTIN XTOUT
1 2 3 4 5 6 7 8 9 10 11
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
P1.3/INT3/BUZ P1.2/INT2/T0CAP P1.1/INT1/T0CLK P1.0/INT0/T0OUT/T0PWM P0.1/ FMF P0.0/ AMF COM0/P6.3 COM1/P6.2 COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.7
S3CK318/ S3FK318 (44-QFP-1010B)
COM5/SEG18/P5.6 COM6/SEG17/P5.5 COM7/SEG16/P5.4 SEG15/P5.3 SEG14/P5.2 SEG13/P5.1 SEG12/P5.0 SEG11/P4.7 SEG10/P4.6 SEG9/P4.5 SEG8/P4.4
Figure 1-5. Pin Assignment (44-QFP-1010B)
1-8
nRESET P3.0/INT4/DAO P3.1/INT5 SEG0/P3.2/INT6 SEG1/P3.3/SI SEG2/P3.4/SO SEG3/P3.5/SCK SEG4/P4.0 SEG5/P4.1 SEG6/P4.2 SEG7/P4.3
12 13 14 15 16 17 18 19 20 21 22
S3CK318/FK318
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. Pin Descriptions Pin Names P0.0 P0.1 P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 Pin Type I I/O Pin Description Input port with bit programmable pins; software assignable pull-up resistors. I/O port with bit programmable pins; Schmitt trigger input or output mode selected by software; Open-drain output mode can be selected by software; software assignable pull-up resistors. I/O port with bit programmable pins; Schmitt trigger input or output mode selected by software; Open-drain output mode can be selected by software; software assignable pull-up resistors. I/O port with bit programmable pins; Schmitt trigger input or output mode selected by software; Open-drain output mode can be selected by software; software assignable pull-up resistors. Circuit Type B-4 E-4 Pin Numbers 39 40 41 42 43 44 1 2 3 4 13 14 Share Pins AMF FMF
INT0/T0OUT/T0PWM
INT1/T0CLK INT2/T0CAP INT3/BUZ AD0 AD1 AD2 AD3 INT4/DAO INT5
I/O
F-16A
I/O
E-5 E-4
P3.2 P3.3 P3.4 P3.5 P4.0-P4.7 I/O I/O port with bit programmable pins; Input or output mode selected by software; Open-drain output mode can be selected by software; software assignable pull-up resistors. Have the same characteristic as port 4
H-32A
15 16 17 18 19-26
SEG0/INT6 SEG1/SI SEG2/SO SEG3/SCK SEG4-SEG11
H-32
P5.0-P5.3 P5.4-P5.7 P6.0-P6.3
I/O
H-32
27-30 31-34 35-38
SEG12-SEG15 SEG16-SEG19/ COM7-COM4 COM3-COM0
I/O
Have the same characteristic as port 4
H-32
1-9
PRODUCT OVERVIEW
S3CK318/FK318
Table 1-1. Pin Descriptions (Continued) Pin Names VDD, VSS XOUT, XIN XTOUT, XTIN TEST nRESET INT0-INT3 INT4 INT5 INT6 SI, SO, SCK AMF FMF T0OUT/T0PWM T0CLK T0CAP BUZ AD0-AD3 DAO COM0-COM3 COM4-COM7 SEG0 SEG1-SEG3 SEG4-SEG11 SEG12-SEG19 Pin Type - - - I I I/O Pin Description Main power supply and Ground Main oscillator pins Sub oscillator pins Test signal input (must be connected to Vss) System reset pin External interrupt input pins Circuit Type - - - - B E-4 E-5 E-4 H-32A H-32A B-4 E-4 Pin Numbers 5, 6 7, 8 11, 10 9 12 41-44 13 14 15 16-18 39 40 41 42 43 44 F-16A E-5 H-32 1-4 13 38-35 34-31 15 16-18 19-26 27-34 Share Pins - - - - - P1.0-P1.3 P3.0/DAO P3.1 P3.2/SEG0 P3.3-P3.5/
SEG1-SEG3
I/O I I/O I/O I/O I/O I/O I/O I/O
Serial I/O interface clock and data signal External AM/FM frequency inputs Timer 0 output and PWM output Timer 0 External clock input Timer 0 Capture input Four frequency output for buzzer sound with main clock or sub clock A/D converter analog input channels D/A converter analog output channel LCD common signal output
P0.0 P0.1 P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT3 P2.0-P2.3 P3.0/INT4 P6.3-P6.0 P5.7-P5.4/ SEG19-SEG16 P3.2/INT6 P3.3-3.5/ SI,SO,SCK P4.0-P4.7 P5.0-P5.7
I/O
LCD segment signal output
H-32A H-32A H-32 H-32
1-10
S3CK318/FK318
PRODUCT OVERVIEW
PIN CIRCUITS
VDD Pull-up Resistor
VDD
Pull-up Enable In
Pull-up Resistor
In
Feedback Enable
Pull-down Enable
Figure 1-6. Pin Circuit Type B (nRESET)
Figure 1-7. Pin Circuit Type B-4 (P0)
VDD
VDD Open drain Enable VDD Pull-up Resistor
Open drain Enable VDD
Pull-up Resistor
P-CH Data
P-CH Data I/O N-CH Output Disable
Output Disable DAC Enable DAC Select N-CH
I/O
From DAC
Figure 1-8. Pin Circuit Type E-4 (P1, P3.1)
Figure 1-9. Pin Circuit Type E-5 (P3.0)
1-11
PRODUCT OVERVIEW
S3CK318/FK318
VDD Pull-up Resistor Pull-up Enable Open-drain Enable Data Output Disable Circuit Type E-4
I/O
ADC Enable ADC Select Data To ADC
Figure 1-10. Pin Circuit Type F-16A (P2)
VLC1
VLC2
VLC3
SEG/COM
OUT
VLC4
VLC5
Vss
Figure 1-11. Pin Circuit Type H-23
1-12
S3CK318/FK318
PRODUCT OVERVIEW
VDD Pull-up Resistor Pull-up Enable I/O
VDD Open-drain Enable Data
LCD OUT Enable VSS
COM/SEG Output Disable
Circuit Type H-23
Figure 1-12. Pin Circuit Type H-32 (P4, P5, and P6)
VDD Pull-up Resistor Pull-up Enable I/O
VDD Open-drain Enable Data
LCD OUT Enable VSS
COM/SEG Output Disable
Circuit Type H-23
Figure 1-13. Pin Circuit Type H-32A (P3.2-P3.5)
1-13
PRODUCT OVERVIEW
S3CK318/FK318
NOTES
1-14
S3CK318/FK318
ADDRESS SPACES
2
OVERVIEW
ADDRESS SPACES
CalmRISC has 20-bit program address lines, PA[19:0], which supports up to 1M words of program memory. The 1M word program memory space is divided into 256 pages and each page is 4K word long as shown in the next page. The upper 8 bits of the program counter, PC[19:12], points to a specific page and the lower 12 bits, PC[11:0], specify the offset address of the page. CalmRISC also has 16-bit data memory address lines, DA[15:0], which supports up to 64K bytes of data memory. The 64K byte data memory space is divided into 256 pages and each page has 256 bytes. The upper 8 bits of the data address, DA[15:8], points to a specific page and the lower 8 bits, DA[7:0], specify the offset address of the page.
PROGRAM MEMORY (ROM)
FFFH 1 Mword
FFFH
4 Kword 000H
256 page 000H
Figure 2-1. Program Memory Organization
2-1
ADDRESS SPACES
S3CK318/FK318
For example, if PC[19:0] = 5F79AH, the page index pointed to by PC is 5FH and the offset in the page is 79AH. If the current PC[19:0] = 5EFFFH and the instruction pointed to by the current PC, i.e., the instruction at the address 5EFFFH is not a branch instruction, the next PC becomes 5E000H, not 5F000H. In other words, the instruction sequence wraps around at the page boundary, unless the instruction at the boundary (in the above example, at 5EFFFH) is a long branch instruction. The only way to change the program page is by long branches (LCALL, LLNK, and LJP), where the absolute branch target address is specified. For example, if the current PC[19:0] = 047ACH (the page index is 04H and the offset is 7ACH) and the instruction pointed to by the current PC, i.e., the instruction at the address 047ACH, is "LJP A507FH" (jump to the program address A507FH), then the next PC[19:0] = A507FH, which means that the page and the offset are changed to A5H and 07FH, respectively. On the other hand, the short branch instructions cannot change the page indices. Suppose the current PC is 6FFFEH and its instruction is "JR 5H" (jump to the program address PC + 5H). Then the next instruction address is 6F003H, not 70003H. In other words, the branch target address calculation also wraps around with respect to a page boundary. This situation is illustrated below:
Page 6FH 000H 001H 002H 003H 004H 005H
FFEH FFFH
JR 5H
Figure 2-2. Relative Jump Around Page Boundary Programmers do not have to manually calculate the offset and insert extra instructions for a jump instruction across page boundaries. The compiler and the assembler for CalmRISC are in charge of producing appropriate codes for it.
2-2
S3CK318/FK318
ADDRESS SPACES
FFFFFH
~ ~
~ ~
0FFFH
Program Memory Area (4K words x 256 page = 1M word)
4K words (8K bytes) 00020H 0001FH 00000H NOTE: For S3CK318, total size of program memory area is 4K words (8K bytes). Vector and Option Area
Figure 2-3. Program Memory Layout From 00000H to 00004H addresses are used for the vector address of exceptions, and 0001EH, 0001FH are used for the option only. Aside from these addresses others are reserved in the vector and option area. Program memory area from the address 00020H to FFFFFH can be used for normal programs. The Program memory size of S3CK318 is 4K word (8K byte), so from the address 00020H to 00FFFH are the program memory area.
2-3
ADDRESS SPACES
S3CK318/FK318
ROM CODE OPTION (RCOD_OPT)
Just after power on, the ROM data located at 0001EH and 0001FH is used as the ROM code option. S3CK318 has ROM code options like the Reset value of Basic timer and Watchdog timer enable. For example, if you program as below: RCOD_OPT1EH, 0x0000 RCOD_OPT1FH, 0xbfff fxx/32 is used as Reset value of basic timer (by bit.14, 13, 12) Watchdog timer is enabled (by bit.11) If you don't program any values in these option areas, then the default value is "1". In these cases, the address 0001EH would be the value of "FFFFH".
2-4
S3CK318/FK318
ADDRESS SPACES
ROM_Code Option (RCOD_OPT) ROM Address: 0001FH MSB .15 .14 .13 .12 .11 .10 .9 .8 LSB
Not used
Not used
Reset value of basic timer clock selection bits (WDTCON.6, .5, .4): 000 = fxx/2 001 = fxx/4 010 = fxx/16 Watchdog timer enable selection bit: 011 = fxx/32 0 = Disable WDT 100 = fxx/128 1 = Enable WDT 101 = fxx/256 110 = fxx/1024 111 = fxx/2048
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
ROM Address: 0001EH MSB .15 .14 .13 .12 .11 .10 .9 .8 LSB
Not used MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
Figure 2-4. ROM Code Option (RCOD_OPT)
2-5
ADDRESS SPACES
S3CK318/FK318
DATA MEMORY ORGANIZATION
The total data memory address space is 64K bytes, addressed by DA[15:0], and divided into 256 pages, Each page consists of 256 bytes as shown below.
FFH 64K bytes
FFH FFFH FFH
256 Byte
00H
256 page 00H 00H 1 page
Figure 2-5. Data Memory Map of CalmRISC8 The data memory page is indexed by SPR and IDH. In data memory index addressing mode, 16-bit data memory address is composed of two 8-bit SPRs, IDH[7:0] and IDL0[7:0] (or IDH[7:0] and IDL1[7:0]). IDH[7:0] points to a page index, and IDL0[7:0] (or IDL1[7:0]) represents the page offset. In data memory direct addressing mode, an 8-bit direct address, adr[7:0], specifies the offset of the page pointed to by IDH[7:0] (See the details for direct addressing mode in the instruction sections). Unlike the program memory organization, data memory address does not wrap around. In other words, data memory index addressing with modification performs an addition or a subtraction operation on the whole 16-bit address of IDH[7:0] and IDL0[7:0] (or IDL1[7:0]) and updates IDH[7:0] and IDL0[7:0] (or IDL1[7:0]) accordingly. Suppose IDH[7:0] is 0FH and IDL0[7:0] is FCH and the modification on the index registers, IDH[7:0] and IDL0[7:0], is increment by 5H, then, after the modification (i.e., 0FFCH + 5 = 1001H), IDH[7:0] and IDL0[7:0] become 10H and 01H, respectively.
2-6
S3CK318/FK318
ADDRESS SPACES
The S3CK318 has 256 bytes of data register address from 0080H to 017FH. The area from 0000H to 007FH is for peripheral control, and LCD RAM area is from 0180H to 0193H.
Page 0 FFH
Data Memory for Genernal Purpose 93H
Page 1 Data Memory for LCD Display
80H 7FH
80H 7FH
Control Register Area
Data Memory for Genernal Purpose
00H 8-bit
00H
Figure 2-6. Data Memory Map of S3CK318
2-7
ADDRESS SPACES
S3CK318/FK318
NOTES
2-8
S3CK318/FK318
REGISTERS
3
OVERVIEW
REGISTERS
The registers of CalmRISC are grouped into 2 parts: general purpose registers and special purpose registers. Table 3-1. General and Special Purpose Registers Registers General Purpose Registers (GPR) Mnemonics R0 R1 R2 R3 Special Purpose Registers (SPR) Group 0 (SPR0) IDL0 IDL1 IDH SR0 Group 1 (SPR1) ILX ILH ILL SR1 Description General Register 0 General Register 1 General Register 2 General Register 3 Lower Byte of Index Register 0 Lower Byte of Index Register 1 Higher Byte of Index Register Status Register 0 Instruction Pointer Link Register for Extended Byte Instruction Pointer Link Register for Higher Byte Instruction Pointer Link Register for Lower Byte Status Register 1 Reset Value Unknown Unknown Unknown Unknown Unknown Unknown Unknown 00H Unknown Unknown Unknown Unknown
GPR's can be used in most instructions such as ALU instructions, stack instructions, load instructions, etc (See the instruction set sections). From the programming standpoint, they have almost no restriction whatsoever. CalmRISC has 4 banks of GPR's and each bank has 4 registers, R0, R1, R2, and R3. Hence, 16 GPR's in total are available. The GPR bank switching can be done by setting an appropriate value in SR0[4:3] (See SR0 for details). The ALU operations between GPR's from different banks are not allowed. SPR's are designed for their own dedicated purposes. They have some restrictions in terms of instructions that can access them. For example, direct ALU operations cannot be performed on SPR's. However, data transfers between a GPR and an SPR are allowed and stack operations with SPR's are also possible (See the instruction sections for details).
3-1
REGISTERS
S3CK318/FK318
INDEX REGISTERS: IDH, IDL0 AND IDL1 IDH in concatenation with IDL0 (or IDL1) forms a 16-bit data memory address. Note that CalmRISC's data memory address space is 64 K byte (addressable by 16-bit addresses). Basically, IDH points to a page index and IDL0 (or IDL1) corresponds to an offset of the page. Like GPR's, the index registers are 2-way banked. There are 2 banks in total, each of which has its own index registers, IDH, IDL0 and IDL1. The banks of index registers can be switched by setting an appropriate value in SR0[2] (See SR0 for details). Normally, programmers can reserve an index register pair, IDH and IDL0 (or IDL1), for software stack operations. LINK REGISTERS: ILX, ILH AND ILL The link registers are specially designed for link-and-branch instructions (See LNK and LRET instructions in the instruction sections for details). When an LNK instruction is executed, the current PC[19:0] is saved into ILX, ILH and ILL registers, i.e., PC[19:16] into ILX[3:0], PC[15:8] into ILH [7:0], and PC[7:0] into ILL[7:0], respectively. When an LRET instruction is executed, the return PC value is recovered from ILX, ILH, and ILL, i.e., ILX[3:0] into PC[19:16], ILH[7:0] into PC[15:8] and ILL[7:0] into PC[7:0], respectively. These registers are used to access program memory by LDC/LDC+ instructions. When an LDC or LDC+ instruction is executed, the (code) data residing at the program address specified by ILX:ILH:ILL will be read into TBH:TBL. LDC+ also increments ILL after accessing the program memory. There is a special core input pin signal, nP64KW, which is reserved for indicating that the program memory address space is only 64 K word. By grounding the signal pin to zero, the upper 4-bit of PC, PC[19:16], is deactivated and therefore the upper 4-bit, PA[19:16], of the program memory address signals from CalmRISC core are also deactivated. By doing so, power consumption due to manipulating the upper 4-bit of PC can be totally eliminated (See the core pin description section for details). From the programmer's standpoint, when nP64KW is tied to the ground level, then PC[19:16] is not saved into ILX for LNK instructions and ILX is not read back into PC[19:16] for LRET instructions. Therefore, ILX is totally unused in LNK and LRET instructions when nP64KW = 0.
3-2
S3CK318/FK318
REGISTERS
STATUS REGISTER 0: SR0 SR0 is mainly reserved for system control functions and each bit of SR0 has its own dedicated function. Table 3-2. Status Register 0 configuration Flag Name eid ie idb grb[1:0] exe ie0 ie1 Bit 0 1 2 4, 3 5 6 7 Description Data memory page selection in direct addressing Global interrupt enable Index register banking selection GPR bank selection Stack overflow/underflow exception enable Interrupt 0 enable Interrupt 1 enable
SR0[0] (or eid) selects which page index is used in direct addressing. If eid = 0, then page 0 (page index = 0) is used. Otherwise (eid = 1), IDH of the current index register bank is used for page index. SR0[1] (or ie) is the global interrupt enable flag. As explained in the interrupt/exception section, CalmRISC has 3 interrupt sources (nonmaskable interrupt, interrupt 0, and interrupt 1) and 1 stack exception. Both interrupt 0 and interrupt 1 are masked by setting SR0[1] to 0 (i.e., ie = 0). When an interrupt is serviced, the global interrupt enable flag ie is automatically cleared. The execution of an IRET instruction (return from an interrupt service routine) automatically sets ie = 1. SR0[2] (or idb) and SR0[4:3] (or grb[1:0]) selects an appropriate bank for index registers and GPR's, respectively as shown below:
R3 R2 R1 R0
R3 R3 R2 R3 R2 R1 R2 R1 R0 R1 R0 Bank 3 Bank 2 R0 Bank 1 Bank 0
grb [1:0]
idb
11 10 01 00
1 0
IDH IDH
IDL0 IDL0 IDL1 IDL1
Figure 3-1. Bank Selection by Setting of GRB Bits and IDB Bit SR0[5] (or exe) enables the stack exception, that is, the stack overflow/underflow exception. If exe = 0, the stack exception is disabled. The stack exception can be used for program debugging in the software development stage. SR0[6] (or ie0) and SR0[7] (or ie1) are enabled, by setting them to 1. Even though ie0 or ie1 are enabled, the interrupts are ignored (not serviced) if the global interrupt enable flag ie is set to 0.
3-3
REGISTERS
S3CK318/FK318
STATUS REGISTER 1: SR1 SR1 is the register for status flags such as ALU execution flag and stack full flag. Table 3-3. Status Register 1: SR1 Flag Name C V Z N SF - Bit 0 1 2 3 4 5, 6, 7 Carry flag Overflow flag Zero flag Negative flag Stack Full flag Reserved Description
SR1[0] (or C) is the carry flag of ALU executions. SR1[1] (or V) is the overflow flag of ALU executions. It is set to 1 if and only if the carry-in into the 8-th bit position of addition/subtraction differs from the carry-out from the 8-th bit position. SR1[2] (or Z) is the zero flag, which is set to 1 if and only if the ALU result is zero. SR1[3] (or N) is the negative flag. Basically, the most significant bit (MSB) of ALU results becomes N flag. Note a load instruction into a GPR is considered an ALU instruction. However, if an ALU instruction touches the overflow flag (V) like ADD, SUB, CP, etc, N flag is updated as exclusive-OR of V and the MSB of the ALU result. This implies that even if an ALU operation results in overflow, N flag is still valid. SR1[4] (or SF) is the stack overflow flag. It is set when the hardware stack is overflowed or under flowed. Programmers can check if the hardware stack has any abnormalities by the stack exception or testing if SF is set (See the hardware stack section for great details). NOTE When an interrupt occurs, SR0 and SR1 are not saved by hardware, so SR0, and SR1 register values must be saved by software.
3-4
S3CK318/FK318
MEMORY MAP
4
OVERVIEW
MEMORY MAP
To support the control of peripheral hardware, the address for peripheral control registers are memory-mapped to page 0 of the RAM. Memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location. In this section, detailed descriptions of the control registers are presented in an easy-to-read format. You can use this section as a quick-reference source when writing application programs. This memory area can be accessed with the whole method of data memory access. -- If SR0 bit 0 is "0" then the accessed register area is always page 0. -- If SR0 bit 0 is "1" then the accessed register page is controlled by the proper IDH register's value. So if you want to access the memory map area, clear the SR0.0 and use the direct addressing mode. This method is used for most cases. This control register is divided into five areas. Here, the system control register area is same in every device.
Control Register 7FH Peripheral Control Register ( 1x 16 or 2 x 8) 70H 6FH Peripheral Control Register (4 x 8) 40H 3FH Port Control Register Area (4 x 8) 20H 1FH Port Data Register Area 10H 0FH System Control Register Area 00H Standard exhortative area Standard area
Figure 4-1. Memory Map Area
4-1
MEMORY MAP
S3CK318/FK318
Table 4-1. Registers Register Name Mnemonic Decimal Hex Reset R/W
Locations 17H-1FH are not mapped. Port 6 data register Port 5 data register Port 4 data register Port 3 data register Port 2 data register Port 1 data register Port 0 data register P6 P5 P4 P3 P2 P1 P0 22 21 20 19 18 17 16 16H 15H 14H 13H 12H 11H 10H 00H 00H 00H 00H 00H 00H 00H R/W R/W R/W R/W R/W R/W R
Locations 0EH-0FH are not mapped. Watchdog timer control register Basic timer counter Interrupt ID register 1 Interrupt priority register 1 Interrupt mask register 1 Interrupt request register 1 Interrupt ID register 0 Interrupt priority register 0 Interrupt mask register 0 Interrupt request register 0 Oscillator control register Power control register WDTCON BTCNT IIR1 IPR1 IMR1 IRQ1 IIR0 IPR0 IMR0 IRQ0 OSCCON PCON 13 12 11 10 9 8 7 6 5 4 3 2 0DH 0CH 0BH 0AH 09H 08H 07H 06H 05H 04H 03H 02H X0H 00H - - 00H - - - 00H - 00H 04H R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W
Locations 00H-01H are not mapped.
NOTES: 1. All the unused and unmapped registers and bits read "0". 2. '-' means undefined. 3. If you want to clear the bit of IRQx, then write the number that you want to clear to IIRx. For example, when clear IRQ0.4 then LD Rx, #04H and LD IIR0, Rx.
4-2
S3CK318/FK318
MEMORY MAP
Table 4-1. Registers (continued) Register Name Mnemonic Decimal Hex Reset R/W
Locations 4BH-4FH are not mapped. Timer 1 counter Timer 1 data register Timer 1 control register T1CNT T1DATA T1CON 74 73 72 4AH 49H 48H 00H FFH 00H R R/W R/W
Locations 45H-47H are not mapped. Timer 0 counter (low byte) Timer 0 counter (high byte) Timer 0 data register (low byte) Timer 0 data register (high byte) Timer 0 control register T0CNTL T0CNTH T0DATAL T0DATAH T0CON 68 67 66 65 64 44H 43H 42H 41H 40H 00H 00H FFH FFH 00H R R R/W R/W R/W
Locations 37H-3FH are not mapped Port 6 control register Port 5 control register (low byte) Port 5 control register (high byte) P6CON P5CONL P5CONH 54 53 52 36H 35H 34H 00H 00H 00H R/W R/W R/W
Locations 32H-33H are not mapped Port 4 control register (low byte) Port 4 control register (high byte) P4CONL P4CONH Location 2FH is not mapped. Port 3 control register C Port 3 control register B Port 3 control register A P3CONC P3CONB P3CONA 45 45 44 2EH 2DH 2CH 00H 00H 00H R/W R/W R/W 49 48 31H 30H 00H 00H R/W R/W
Locations 2AH-2BH are not mapped Port 2 pull-up control register Port 2 control register P2PUR P2CON Location 27H is not mapped Port 1 interrupt edge selection register Port 1 pull-up control register Port 1 control register P1EDGE P1PUR P1CON 38 37 36 26H 25H 24H 00H 00H 00H R/W R/W R/W 41 40 29H 28H 00H 00H R/W R/W
Locations 21H-23H are not mapped Port 0 pull-up control register
NOTES: 1. All unused and unmapped registers and bits read "0". 2. '-' means undefined.
P0PUR
32
20H
00H
R/W
4-3
MEMORY MAP
S3CK318/FK318
Table 4-1. Registers (continued) Register Name Mnemonic Decimal Hex Reset R/W
Locations 7DH-7FH are not mapped Frequency Counter 2 (high byte) Frequency Counter 1 (mid byte) Frequency Counter 0 (low byte) Frequency counter mode register Frequency counter control register FCNT2 FCNT1 FCNT0 FCMOD FCCON Location 77H is not mapped D/A converter data register (low byte) D/A converter data register (high byte) D/A converter control register DADATAL DADATAH DACON 118 117 116 76H 75H 74H 00H 00H 00H R/W R/W R/W 124 123 122 121 120 7CH 7BH 7AH 79H 78H 00H 00H 00H 00H 00H R R R R/W R/W
Locations 72H-73H are not mapped Battery level detector control register Watch timer control register BLDCON WTCON 113 112 71H 70H 00H 00H R/W R/W
Locations 64H-6FH are not mapped LCD Port Control Register 2 LCD Port Control Register 1 LCD Port Control Register 0 LCD mode control register LPOT2 LPOT1 LPOT0 LMOD Location 5FH is not mapped A/D Converter data register (low byte) A/D Converter data register (high byte) A/D Converter control register ADDATAL ADDATAH ADCON Location 5BH is not mapped Serial I/O data register Serial I/O pre-scale register Serial I/O control register SIODATA SIOPS SIOCON 90 89 88 5AH 59H 58H 00H 00H 00H R/W R/W R/W 94 93 92 5EH 5DH 5CH - - 00H R R R/W 99 98 97 96 63H 62H 61H 60H 00H 00H 00H 00H R/W R/W R/W R/W
Locations 50H-57H are not mapped
NOTES 1. All unused and unmapped registers and bits read "0". 2. "-" means undefined.
4-4
S3CK318/FK318
HARDWARE STACK
5
OVERVIEW
HARDWARE STACK
The hardware stack in CalmRISC has two usages: -- To save and restore the return PC[19:0] on LCALL, CALLS, RET, and IRET instructions. -- Temporary storage space for registers on PUSH and POP instructions. When PC[19:0] is saved into or restored from the hardware stack, the access should be 20 bits wide. On the other hand, when a register is pushed into or popped from the hardware stack, the access should be 8 bits wide. Hence, to maximize the efficiency of the stack usage, the hardware stack is divided into 3 parts: the extended stack bank (XSTACK, 4 bits wide), the odd bank (8 bits wide), and the even bank (8 bits wide).
Hardware Stack 5 3 Level 0 Level 1 Level 2 0 7 0 7 0
Stack Pointer SPTR [5:0] 1 0
Stack Level Pointer
Odd or Even Bank Selector
Level 14 Level 15 XSTACK Odd Bank Even Bank
Figure 5-1. Hardware Stack
5-1
HARDWARE STACK
S3CK318/FK318
The top of the stack (TOS) is pointed to by a stack pointer, called sptr[5:0]. The upper 5 bits of the stack pointer, sptr[5:1], points to the stack level into which either PC[19:0] or a register is saved. For example, if sptr[5:1] is 5H or TOS is 5, then level 5 of XSTACK is empty and either level 5 of the odd bank or level 5 of the even bank is empty. In fact, sptr[0], the stack bank selection bit, indicates which bank(s) is empty. If sptr[0] = 0, both level 5 of the even and the odd banks are empty. On the other hand, if sptr[0] = 1, level 5 of the odd bank is empty, but level 5 of the even bank is occupied. This situation is well illustrated in the figure below.
Level 0 Level 1 Level 2 Level 3 Level 4 Level 5
SPTR [5:0] 5 10 001010 Stack Level Pointer Bank Selector
Level 15 XSTACK Odd Bank Even Bank
Level 0 Level 1 Level 2 Level 3 Level 4 Level 5
SPTR [5:0] 5 10 001011 Stack Level Pointer Bank Selector
Level 15 XSTACK Odd Bank Even Bank
Figure 5-2. Even and Odd Bank Selection Example As can be seen in the above example, sptr[5:1] is used as the hardware stack pointer when PC[19:0] is pushed or popped and sptr[5:0] as the hardware stack pointer when a register is pushed or popped. Note that XSTACK is used only for storing and retrieving PC[19:16]. Let us consider the cases where PC[19:0] is pushed into the hardware stack (by executing LCALL/CALLS instructions or by interrupts/exceptions being served) or is retrieved from the hardware stack (by executing RET/IRET instructions). Regardless of the stack bank selection bit (sptr[0]), TOS of the even bank and the odd bank store or return PC[7:0] or PC[15:8], respectively. This is illustrated in the following figures.
5-2
S3CK318/FK318
HARDWARE STACK
Level 0
SPTR [5:0]
5 10 001010 Stack Level Pointer
Level 0
SPTR [5:0]
5 10 001011 Stack Level Pointer
Level 5 Level 6 Bank Selector
Level 5 Level 6 Bank Selector
Level 15 XSTACK Odd Bank Even Bank by Executing CALL, CALLS or Interrupts/Exceptions
Level 15 XSTACK Odd Bank Even Bank by Executing CALL, CALLS or Interrupts/Exceptions
by Executing RET, IRET
by Executing RET, IRET
Level 0
SPTR [5:0]
5 10 001100 Stack Level Pointer
Level 0
SPTR [5:0]
5 10 001101 Stack Level Pointer
Level 5 PC[19:16] Level 6
PC[15:8]
PC[7:0]
Level 5 PC[19:16] Bank Selector Level 6
PC[7:0] PC[15:8]
Bank Selector
Level 15 XSTACK Odd Bank Even Bank
Level 15 XSTACK Odd Bank Even Bank
Figure 5-3. Stack Operation with PC [19:0] As can be seen in the figures, when stack operations with PC[19:0] are performed, the stack level pointer sptr[5:1] (not sptr[5:0]) is either incremented by 1 (when PC[19:0] is pushed into the stack) or decremented by 1 (when PC[19:0] is popped from the stack). The stack bank selection bit (sptr[0]) is unchanged. If a CalmRISC core input signal nP64KW is 0, which signifies that only PC[15:0] is meaningful, then any access to XSTACK is totally deactivated from the stack operations with PC. Therefore, XSTACK has no meaning when the input pin signal, nP64KW, is tied to 0. In that case, XSTACK doesn't have to even exist. As a matter of fact, XSTACK is not included in CalmRISC core itself and it is interfaced through some specially reserved core pin signals (nPUSH, nSTACK, XHSI[3:0], XSHO[3:0]), if the program address space is more than 64 K words (See the core pin signal section for details). With regards to stack operations with registers, a similar argument can be made. The only difference is that the data written into or read from the stack are a byte. Hence, the even bank and the odd bank are accessed alternately as shown below.
5-3
HARDWARE STACK
S3CK318/FK318
Level 0
SPTR [5:0]
5 10 001010 Stack Level Pointer
Level 0
SPTR [5:0]
5 10 001011 Stack Level Pointer
Level 5 Level 6 Bank Selector
Level 5 Level 6 Bank Selector
Level 15 XSTACK Odd Bank Even Bank
Level 15 XSTACK Odd Bank Even Bank
POP Register
PUSH Register
POP Register
PUSH Register
Level 0
SPTR [5:0]
5 10 001011 Stack Level Pointer
Level 0
SPTR [5:0]
5 10 001100 Stack Level Pointer
Level 5 Level 6
Register
Level 5 Bank Selector Level 6
Register
Bank Selector
Level 15 XSTACK Odd Bank Even Bank
Level 15 XSTACK Odd Bank Even Bank
Figure 5-4. Stack Operation with Registers When the bank selection bit (sptr[0]) is 0, then the register is pushed into the even bank and the bank selection bit is set to 1. In this case, the stack level pointer is unchanged. When the bank selection bit (sptr[0]) is 1, then the register is pushed into the odd bank, the bank selection bit is set to 0, and the stack level pointer is incremented by 1. Unlike the push operations of PC[19:0], any data are not written into XSTACK in the register push operations. This is illustrated in the example figures. When a register is pushed into the stack, sptr[5:0] is incremented by 1 (not the stack level pointer sptr[5:1]). The register pop operations are the reverse processes of the register push operations. When a register is popped out of the stack, sptr[5:0] is decremented by 1 (not the stack level pointer sptr[5:1]). Hardware stack overflow/underflow happens when the MSB of the stack level pointer, sptr[5], is 1. This is obvious from the fact that the hardware stack has only 16 levels and the following relationship holds for the stack level pointer in a normal case. Suppose the stack level pointer sptr[5:1] = 15 (or 01111B in binary format) and the bank selection bit sptr[0] = 1. Here if either PC[19:0] or a register is pushed, the stack level pointer is incremented by 1. Therefore, sptr[5:1] = 16 (or 10000B in binary format) and sptr[5] = 1, which implies that the stack is overflowed. The situation is depicted in the following.
5-4
S3CK318/FK318
HARDWARE STACK
SPTR [5:0]
5 10 011111 Level 0 Level 1
Level 14 Level 15 XSTACK Odd Bank PUSH Register Even Bank PUSH PC [19:0]
SPTR [5:0]
5 10 100000 Level 0 Level 1
SPTR [5:0]
5 10 100001
Level 0 Level 1
PC[7:0]
Level 14 Level 15 Register XSTACK Odd Bank Even Bank
Level 14 Level 15 PC[19:16]
PC[15:8]
XSTACK Odd Bank
Even Bank
Figure 5-5. Stack Overflow
5-5
HARDWARE STACK
S3CK318/FK318
The first overflow happens due to a register push operation. As explained earlier, a register push operation increments sptr[5:0] (not sptr[5:1]) , which results in sptr[5] = 1, sptr[4:1] = 0 and sptr[0] = 0. As indicated by sptr[5] = 1, an overflow happens. Note that this overflow doesn't overwrite any data in the stack. On the other hand, when PC[19:0] is pushed, sptr[5:1] is incremented by 1 instead of sptr[5:0], and as expected, an overflow results. Unlike the first overflow, PC[7:0] is pushed into level 0 of the even bank and the data that has been there before the push operation is overwritten. A similar argument can be made about stack underflows. Note that any stack operation, which causes the stack to overflow or underflow, doesn't necessarily mean that any data in the stack are lost, as is observed in the first example. In SR1, there is a status flag, SF (Stack Full Flag), which is exactly the same as sptr[5]. In other words, the value of sptr[5] can be checked by reading SF (or SR1[4]). SF is not a sticky flag in the sense that if there was a stack overflow/underflow but any following stack access instructions clear sptr[5] to 0, then SF = 0 and programmers cannot tell whether there was a stack overflow/underflow by reading SF. For example, if a program pushes a register 64 times in a row, sptr[5:0] is exactly the same as sptr[5:0] before the push sequence. Therefore, special attention should be paid. Another mechanism to detect a stack overflow/underflow is through a stack exception. A stack exception happens only when the execution of any stack access instruction results in SF = 1 (or sptr[5] = 1). Suppose a register push operation makes SF = 1 (the SF value before the push operation doesn't matter). Then the stack exception due to the push operation is immediately generated and served If the stack exception enable flag (exe of SR0) is 1. If the stack exception enable flag is 0, then the generated interrupt is not served but pending. Sometime later when the stack exception enable flag is set to 1, the pending exception request is served even if SF = 0. More details are available in the stack exception section.
5-6
S3CK318/FK318
EXCEPTIONS
6
OVERVIEW
EXCEPTIONS
Exceptions in CalmRISC are listed in the table below. Exception handling routines, residing at the given addresses in the table, are invoked when the corresponding exception occurs. The start address of each exception routine is specified by concatenation 0H (leading 4 bits of 0) and the 16-bit data in the exception vector listed in the table. For example, the interrupt service routine for IRQ[0] starts from 0H:PM[00002H]. Note that ":"means concatenation and PM[*] stands for the 16-bit content at the address * of the program memory. Aside from the exception due to reset release, the current PC is pushed in the stack on an exception. When an exception is executed due to IRQ[1:0]/IEXP, the global interrupt enable flag, ie bit (SR0[1]), is set to 0, whereas ie is set to 1 when IRET or an instruction that explicitly sets ie is executed. Table 6-1. Exceptions Name Reset - IRQ[0] IRQ[1] IEXP - - -
NOTE:
Address 00000H 00001H 00002H 00003H 00004H 00005H 00006H 00007H
Priority 1st - 3rd 4th 2nd - - -
Description Exception due to reset release. Reserved Exception due to nIRQ[0] signal. Maskable by setting ie/ie0. Exception due to nIRQ[1] signal. Maskable by setting ie/ie1. Exception due to stack full. Maskable by setting exe. Reserved. Reserved. Reserved.
Break mode due to BKREQ has a higher priority than all the exceptions above. That is, when BKREQ is active, even the exception due to reset release is not executed.
HARDWARE RESET When Hardware Reset is active (the reset input signal pin nRES = 0), the control pins in the CalmRISC core are initialized to be disabled, and SR0 and sptr (the hardware stack pointer) are initialized to be 0. Additionally, the interrupt sensing block is cleared. When Hardware Reset is released (nRES = 1), the reset exception is executed by loading the JP instruction in IR (Instruction Register) and 0h:0000h in PC. Therefore, when Hardware Reset is released, the "JP {0h:PM[00000h]}" instruction is executed.
6-1
EXCEPTIONS
S3CK318/FK318
IRQ[0] EXCEPTION When a core input signal nIRQ[0] is low, SR0[6] (ie0) is high, and SR0[1] (ie) is high, IRQ[0] exception is generated, and this will load the CALL instruction in IR (Instruction Register) and 0h:0002h in PC. Therefore, on an IRQ[0] exception, the "CALL {0h:PM[00002h]}" instruction is executed. When the IRQ[0] exception is executed, SR0[1] (ie) is set to 0. IRQ[1] EXCEPTION (LEVEL-SENSITIVE) When a core input signal nIRQ[1] is low, SR0[7] (ie1) is high, and SR0[1] (ie) is high, IRQ[1] exception is generated, and this will load the CALL instruction in IR (Instruction Register) and 0h:0003h in PC. Therefore, on an IRQ[1] exception, the "CALL {0h:PM[00003h]}" instruction is executed. When the IRQ[1] exception is executed, SR0[1] (ie) is set to 0. HARDWARE STACK FULL EXCEPTION A Stack Full exception occurs when a stack operation is performed and as a result of the stack operation sptr[5] (SF) is set to 1. If the stack exception enable bit, exe (SR0[5]), is 1, the Stack Full exception is served. One exception to this rule is when nNMI causes a stack operation that sets sptr[5] (SF), since it has higher priority. Handling a Stack Full exception may cause another Stack Full exception. In this case, the new exception is ignored. On a Stack Full exception, the CALL instruction is loaded in IR (Instruction Register) and 0h:0004h in PC. Therefore, when the Stack Full exception is activated, the "CALL {0h:PM[00004h]}" instruction is executed. When the exception is executed, SR0[1] (ie) is set to 0. BREAK EXCEPTION Break exception is reserved only for an in-circuit debugger. When a core input signal, BKREQ, is high, the CalmRISC core is halted or in the break mode, until BKREQ is deactivated. Another way to drive the CalmRISC core into the break mode is by executing a break instruction, BREAK. When BREAK is fetched, it is decoded in the fetch cycle (IF stage) and the CalmRISC core output signal nBKACK is generated in the second cycle (ID/MEM stage). An in-circuit debugger generates BKREQ active by monitoring nBKACK to be active. BREAK instruction is exactly the same as the NOP (no operation) instruction except that it does not increase the program counter and activates nBKACK in the second cycle (or ID/MEM stage of the pipeline). There, once BREAK is encountered in the program execution, it falls into a deadlock. BREAK instruction is reserved for in-circuit debuggers only, so it should not be used in user programs.
6-2
S3CK318/FK318
EXCEPTIONS
EXCEPTIONS (or INTERRUPTS)
LEVEL RESET NMI IVEC0
VECTOR 0000H 0001H 0002H
SOURCE RESET Not used Timer 0 match/capture Timer 0 overflow Timer 1 match FC counting ends SIO Basic timer overflow
RESET (CLEAR) H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W
IVEC1
0003H
Watch timer INT0 INT1 INT2 INT3 INT4 INT5 INT6
SF_EXCEP
0004H
Stack full INT
NOTES: 1. RESET has the highest priority for an interrupt level, followed by SF_EXCEP, IVEC0 and IVEC1. 2. In the case of IVEC0 and IVEC1, one interrupt vector has several interrupt sources. The priority of the sources is controlled by setting the IPR register. 3. External interrupts are triggered by rising or falling edge, depending on the corresponding control register setting. 4. After system reset, the IPR register is in unknown status, so user must set the IPR register with proper value. 5. The pending bit is cleared by hardware when CPU reads the IIR registser value.
Figure 6-1. Interrupt Structure
6-3
EXCEPTIONS
S3CK318/FK318
Clear (when writing clear bit value to bit.2. 1. 0) ex) LD R0, #x5H LD IIR0, R0 IRQ0.5 is cleared
IIR0
Timer 0 match/capture Timer 0 overflow Timer 1 match FC counting ends SIO Basic Timer overflow Not used Not used
IRQ0.0 IRQ0.1 IRQ0.2 IRQ0.3 IRQ0.4 IRQ0.5 IRQ0.6 IRQ0.7 IMR0 IPR0 IVEC0 IMR0 Logic IPR0 Logic
STOP & IDLE Release
CPU
Watch timer INT0 INT1 INT2 INT3 INT4 INT5 INT6
IRQ1.0 IRQ1.1 IRQ1.2 IRQ1.3 IRQ1.4 IRQ1.5 IRQ1.6 IRQ1.7
IMR1
IPR1 IVEC1
IMR1 Logic
IPR1 Logic
Clear (when writing clear bit value to bit.2. 1. 0) ex) LD R0, #x2H LD IIR1, R0 IRQ1.2 is cleared NOTE:
IIR1
The IRQ register value is cleared by H/W when the IIR register is read by the programmer in an interrupt service routine. However, if you want to clear by S/W, then write the proper value to the IIR register like as in the example above. To clear all the bits of IRQx register at one time write "#08h" to the IIRx register.
Figure 6-2. Interrupt Block Diagram
6-4
S3CK318/FK318
EXCEPTIONS
INTERRUPT MASK REGISTERS
Interrupt Mask Register0 (IMR0) 05H, R/W, Reset: 00H .7 .6 .5 .4 .3 .2 .1 .0
IRQ0.4 IRQ0.5 Not used Not used IRQ0.3 IRQ0.2 IRQ0.1
IRQ0.0
Interrupt Mask Register1 (IMR1) 09H, R/W, Reset: 00H .7 .6 .5 .4 .3 .2 .1 .0
IRQ1.4 IRQ1.5 IRQ1.6 IRQ1.7 Interrupt request enable bits: 0 1 NOTE: Disable interrupt request Enable interrupt request IRQ1.3 IRQ1.2 IRQ1.1
IRQ1.0
If you want to change the value of the IMR register, then you first make disable global INT by DI instruction, and change the value of the IMR register.
Figure 6-3. Interrupt Mask Register
6-5
EXCEPTIONS
S3CK318/FK318
INTERRUPT PRIORITY REGISTER
IPR GROUP A
IPR GROUP B
IPR GROUP C
IRQx.0
IRQx.1
IRQx.2
IRQx.3 IRQx.4
IRQx.5
IRQx.6
IRQx.7
Interrupt Priority Registers (IPR0:06H,IPR1:0AH, R/W ) .7 .6 .5 .4 .3 .2 .1 .0
Group priority: .7 .4 .1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Not used B>C>A A>B>C B>A>C C>A>B C>B>A A>C>B Not used GROUP A 0 = IRQx.0 > IRQx.1 1 = IRQx.1 > IRQx.0 GROUP B 0 = IRQx.2 > (IRQx.3,IRQx.4) 1 = (IRQx.3,IRQx.4) > IRQx.2 SUBGROUP B 0 = IRQx.3 > IRQx.4 1 = IRQx.4 > IRQx.3 GROUP C 0 = IRQx.5 > (IRQx.6,IRQx.7) 1 = (IRQx.6,IRQx.7) > IRQx.5 SUBGROUP C 0 = IRQx.6 > IRQx.7 1 = IRQx.7 > IRQx.6 NOTES: 1. If you want to change the value of the IPR register, then you first make disable global INT by DI instruction, and change the value of the IPR register. After reset, IPR register is unknown status, so user must set the IPR register with proper value. 2. Where 'x' is '0' or '1'.
Figure 6-4. Interrupt Priority Register
6-6
S3CK318/FK318
EXCEPTIONS
FPROGRAMMING TIP -- Interrupt Programming Tip 1
Jumped from vector 2 PUSH PUSH LD CP JR CP JR CP JP JP CP JP JP CP JR CP JP JP CP JP JP
*
LTE05
LTE03
LTE01
SR1 R0 R0, IIR0 R0, #03h ULE, LTE03 R0, #05h ULE, LTE05 R0, #06h EQ, IRQ6_srv T, IRQ7_srv R0, #04 EQ, IRQ4_srv T, IRQ5_srv R0, #01 ULE, LTE01 R0, #02 EQ, IRQ2_srv T, IRQ3_srv R0, #00h EQ, IRQ0_srv T, IRQ1_srv ; service for IRQ0
IRQ0_srv POP POP IRET IRQ1_srv
* *
R0 SR1 ; service for IRQ1
POP POP IRET
* *
R0 SR1
IRQ7_srv
* *
; service for IRQ7
POP POP IRET
R0 SR1
NOTE If the SR0 register is changed in the interrupt service routine, then the SR0 register must be pushed and popped in the interrupt service routine.
6-7
EXCEPTIONS
S3CK318/FK318
FPROGRAMMING TIP -- Interrupt Programming Tip 2
Jumped from vector 2 PUSH PUSH PUSH LD SL LD ADD INCC LD LD LRET LJP LJP LJP LJP LJP LJP LJP LJP
* *
SR1 R0 R1 R0, IIR0 R0 R1, # < TBL_INTx R0, # > TBL_INTx R1 ILH, R1 ILL, R0 IRQ0_svr IRQ1_svr IRQ2_svr IRQ3_svr IRQ4_svr IRQ5_svr IRQ6_svr IRQ7_svr ; service for IRQ0
TBL_INTx
IRQ0_srv
POP POP POP IRET IRQ1_srv
* *
R1 R0 SR1 ; service for IRQ1
POP POP POP IRET
* *
R1 R0 SR1
IRQ7_srv
* *
; service for IRQ7
POP POP POP IRET
R1 R0 SR1
NOTE 1. 2. If the SR0 register is changed in the interrupt service routine, then the SR0 register must be pushed and popped in the interrupt service routine. Above example is assumed that ROM size is less than 64K-word and all the LJP instructions in the jump table (TBL_INTx) is in the same page.
6-8
S3CK318/FK318
INSTRUCTION SET
7
OVERVIEW
GLOSSARY Notation GPR SPR adr:N @idm (adr:N) cc:4 imm:N & | ~ ^ N**M (N)M
INSTRUCTION SET
This chapter describes the CalmRISC instruction set and the details of each instruction are listed in alphabetical order. The following notations are used for the description. Table 7-1. Instruction Notation Conventions Interpretation Operand N. N can be omitted if there is only one operand. Typically, is the destination (and source) operand and is a source operand. General Purpose Register Special Purpose Register (IDL0, IDL1, IDH, SR0, ILX, ILH, ILL, SR1) N-bit address specifier Content of memory location pointed by ID0 or ID1 Content of memory location specified by adr:N 4-bit condition code. Table 7-6 describes cc:4. N-bit immediate number Bit-wise AND Bit-wise OR Bit-wise NOT Bit-wise XOR Mth power of N M-based number N
As additional note, only the affected flags are described in the tables in this section. That is, if a flag is not affected by an operation, it is NOT specified.
7-1
INSTRUCTION SET
S3CK318/FK318
INSTRUCTION SET MAP
Table 7-2. Overall Instruction Set Map IR [15:13,7:2] 000 xxxxxx 001 xxxxxx [12:10]000 ADD GPR, #imm:8 ADD GPR, @idm ADD GPR, adr:8 ADC GPR, adr:8 ADD GPR, GPR ADC GPR, GPR invalid AND GPR, GPR SLA/SL/ RLC/RL/ SRA/SR/ RRC/RR/ GPR 001 SUB GPR, #imm:8 SUB GPR, @idm SUB GPR, adr:8 SBC GPR, adr:8 SUB GPR, GPR SBC GPR, GPR invalid OR GPR, GPR INC/INCC/ DEC/ DECC/ COM/ COM2/ COMC GPR LD GPR, SPR 010 CP GPR, #imm8 CP GPR, @idm CP GPR, adr:8 CPC GPR, adr:8 CP GPR, GPR CPC GPR, GPR invalid XOR GPR, GPR invalid 011 LD GPR, #imm:8 LD GPR, @idm LD GPR, adr:8 LD adr:8, GPR 100 TM GPR, #imm:8 LD @idm, GPR 101 AND GPR, #imm:8 AND GPR, @idm 110 OR GPR, #imm:8 OR GPR, @idm 111 XOR GPR, #imm:8 XOR GPR, @idm
010 xxxxxx
BITT adr:8.bs
BITS adr:8.bs
011 xxxxxx
BITR adr:8.bs
BITC adr:8.bs
100 000000
BMS/BMC LD SPR0, #imm:8 invalid
AND GPR, adr:8
OR GPR, adr:8
XOR GPR, adr:8
100 000001
100 000010 100 000011
invalid invalid
100 00010x
invalid
100 00011x
LD SPR, GPR
SWAP GPR, SPR invalid LD GPR, GPR
LD TBH/TBL, GPR invalid LD GPR, TBH/TBL
100 00100x 100 001010
PUSH SPR POP SPR PUSH GPR POP GPR
7-2
S3CK318/FK318
INSTRUCTION SET
Table 7-2. Overall Instruction Set Map (Continued) IR 100 001011 [12:10]000 POP 001 invalid 010 LDC 011 invalid 100 LD SPR0, #imm:8 101 AND GPR, adr:8 110 OR GPR, adr:8 111 XOR GPR, adr:8
100 00110x
RET/LRET/I RET/NOP/ BREAK invalid LD GPR:bank, GPR:bank invalid
invalid
invalid
invalid
100 00111x 100 01xxxx
invalid AND SR0, #imm:8 invalid
invalid OR SR0, #imm:8 invalid
invalid BANK #imm:2 invalid
100 100000 100 110011 100 1101xx 100 1110xx 100 1111xx [15:10] 101 xxx 110 0xx 110 1xx 111 xxx
NOTE:
LCALL cc:4, imm:20 (2-word instruction) LLNK cc:4, imm:20 (2-word instruction) LJP cc:4, imm:20 (2-word instruction) JR cc:4, imm:9 CALLS imm:12 LNKS imm:12 CLD GPR, imm:8 / CLD imm:8, GPR / JNZD GPR, imm:8 / SYS #imm:8 / COP #imm:12
"invalid" - invalid instruction.
7-3
INSTRUCTION SET
S3CK318/FK318
Table 7-3. Instruction Encoding Instruction ADD GPR, #imm:8 SUB GPR, #imm:8 CP GPR, #imm:8 LD GPR, #imm:8 TM GPR, #imm:8 AND GPR, #imm:8 OR GPR, #imm:8 XOR GPR, #imm:8 ADD GPR, @idm SUB GPR, @idm CP GPR, @idm LD GPR, @idm LD @idm, GPR AND GPR, @idm OR GPR, @idm XOR GPR, @idm ADD GPR, adr:8 SUB GPR, adr:8 CP GPR, adr:8 LD GPR, adr:8 BITT adr:8.bs BITS adr:8.bs ADC GPR, adr:8 SBC GPR, adr:8 CPC GPR, adr:8 LD adr:8, GPR BITR adr:8.bs BITC adr:8.bs 011 010 001 15 14 000 13 12 11 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 10 11 000 001 010 011 10 11 bs GPR adr[7:0] bs GPR adr[7:0] GPR idx mod offset[4:0] 10 9 8 7 6 5 4 3 2 1 0
GPR
imm[7:0]
7-4
S3CK318/FK318
INSTRUCTION SET
Table 7-3. Instruction Encoding (Continued) Instruction ADD GPRd, GPRs SUB GPRd, GPRs CP GPRd, GPRs BMS/BMC ADC GPRd, GPRs SBC GPRd, GPRs CPC GPRd, GPRs invalid invalid AND GPRd, GPRs OR GPRd, GPRs XOR GPRd, GPRs invalid ALUop1 ALUop2 invalid LD SPR, GPR LD GPR, SPR SWAP GPR, SPR LD TBL, GPR LD TBH, GPR PUSH SPR POP SPR invalid PUSH GPR POP GPR LD GPRd, GPRs LD GPR, TBL LD GPR, TBH POP LDC @IL LDC @IL+ Invalid
NOTE: "x" means not applicable.
15
14 100
13
12
11 000 001 010 011 000 001 010 011 ddd 000 001 010 011 000 001
10
9
8
7
6
5
4
3
2
1
0
GPRd
000000
GPRs
000001
000010 000011
GPR GPR xx GPR GPR GPR GPR
00010
ALUop1 ALUop2 xxx
010-011 000 001 010 011
00011
SPR SPR SPR x x 0 1 SPR SPR xxx x x
000 001 010-011 000 001 010 011
xx xx xx GPR GPR GPRd GPR
00100
001010
GPR GPR GPRs 0 1 x x xx 0 1 x x xx
000 010
xx
001011
001, 011
7-5
INSTRUCTION SET
S3CK318/FK318
Table 7-3. Instruction Encoding (Concluded) Instruction MODop1 Invalid Invalid AND SR0, #imm:8 OR SR0, #imm:8 BANK #imm:2 15-13 100 12 11 000 001-011 000 001 010 011 10 9 xx xx xx imm[7:6] imm[7:6] xx x imm [1:0] Invalid LCALL cc, imm:20 LLNK cc, imm:20 LJP cc, imm:20 LD SPR0, #imm:8 AND GPR, adr:8 OR GPR, adr:8 XOR GPR, adr:8 JR cc, imm:9 CALLS imm:12 LNKS imm:12 CLD GPR, imm:8 CLD imm:8, GPR JNZD GPR, imm:8 SYS #imm:8 COP #imm:12 1 111 101 110
imm [8]
8
7
6
5 00110
4
3
2
1 MODop1 xxx
0
2nd word -
01
xxxxxx imm[5:0]
xxx
0
xxxx cc
10000000-11001111 1101 imm[19:16] imm[15:0]
1
00 01 10 11 cc
SPR0 GPR
IMM[7:0] ADR[7:0]
-
imm[7:0] imm[11:0]
0 1 0 00 01 10 11 GPR GPR GPR xx
imm[7:0]
imm[11:0]
NOTES: 1. "x" means not applicable. 2. There are several MODop1 codes that can be used, as described in table 7-9. 3. The operand 1(GPR) of the instruction JNZD is Bank 3's register.
7-6
S3CK318/FK318
INSTRUCTION SET
Table 7-4. Index Code Information ("idx") Symbol ID0 ID1 Code 0 1 Index 0 IDH:IDL0 Index 1 IDH:IDL1 Description
Table 7-5. Index Modification Code Information ("mod") Symbol @IDx + offset:5 @[IDx - offset:5] Code 00 01 Function DM[IDx], IDx IDx + offset DM[IDx + (2's complement of offset:5)], IDx IDx + (2's complement of offset:5) @[IDx + offset:5]! @[IDx - offset:5]!
NOTE:
10 11
DM[IDx + offset], IDx IDx DM[IDx + (2's complement of offset:5)], IDx IDx
Carry from IDL is propagated to IDH. In case of @[IDx - offset:5] or @[IDx - offset:5]!, the assembler should convert offset:5 to the 2's complement format to fill the operand field (offset[4:0]). Furthermore, @[IDx - 0] and @[IDx - 0]! are converted to @[IDx + 0] and @[IDx + 0]!, respectively.
Table 7-6. Condition Code Information ("cc") Symbol (cc:4) Blank NC or ULT C or UGE Z or EQ NZ or NE OV ULE UGT ZP MI PL ZN SF EC0-EC2
NOTE:
Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101-1111 always
Function
C = 0, unsigned less than C = 1, unsigned greater than or equal to Z = 1, equal to Z = 0, not equal to V = 1, overflow - signed value ~C | Z, unsigned less than or equal to C & ~Z, unsigned greater than N = 0, signed zero or positive N = 1, signed negative ~N & ~Z, signed positive Z | N, signed zero or negative Stack Full EC[0] = 1/EC[1] = 1/EC[2] = 1
EC[2:0] is an external input (CalmRISC core's point of view) and used as a condition.
7-7
INSTRUCTION SET
S3CK318/FK318
Table 7-7. "ALUop1" Code Information Symbol SLA SL RLC RL SRA SR RRC RR Code 000 001 010 011 100 101 110 111 arithmetic shift left shift left rotate left with carry rotate left arithmetic shift right shift right rotate right with carry rotate right Function
Table 7-8. "ALUop2" Code Information Symbol INC INCC DEC DECC COM COM2 COMC - Code 000 001 010 011 100 101 110 111 increment increment with carry decrement decrement with carry 1's complement 2's complement 1's complement with carry reserved Function
Table 7-9. "MODop1" Code Information Symbol LRET RET IRET NOP BREAK - - - Code 000 001 010 011 100 101 110 111 return by IL return by HS return from interrupt (by HS) no operation reserved for debugger use only reserved reserved reserved Function
7-8
S3CK318/FK318
INSTRUCTION SET
QUICK REFERENCE
Operation AND OR XOR ADD SUB CP ADC SBC CPC TM BITS BITR BITC BITT BMS/BMC PUSH POP PUSH POP POP SLA SL RLC RL SRA SR RRC RR INC INCC DEC DECC COM COM2 COMC - GPR - - SPR - - GPR - - GPR R3 #imm:8 adr:8.bs GPR GPR adr:8 op1 GPR op2 adr:8 #imm:8 GPR @idm op1 op1 & op2 op1 op1 | op2 op1 op1 ^ op2 op1 op1 + op2 op1 op1 + ~op2 + 1 op1 + ~op2 + 1 op1 op1 + op2 + c op1 op1 + ~op2 + c op1 + ~op2 + c op1 & op2 op1 (op2[bit] 1) op1 (op2[bit] 0) op1 ~(op2[bit]) z ~(op2[bit]) TF 1 / 0 HS[sptr] GPR, (sptr sptr + 1) GPR HS[sptr - 1], (sptr sptr - 1) HS[sptr] SPR, (sptr sptr + 1) SPR HS[sptr - 1], (sptr sptr - 1) sptr sptr - 2 c op1[7], op1 {op1[6:0], 0} c op1[7], op1 {op1[6:0], 0} c op1[7], op1 {op1[6:0], c} c op[7], op1 {op1[6:0], op1[7]} c op[0], op1 {op1[7],op1[7:1]} c op1[0], op1 {0, op1[7:1]} c op1[0], op1 {c, op1[7:1]} c op1[0], op1 {op1[0], op1[7:1]} op1 op1 + 1 op1 op1 + c op1 op1 + 0FFh op1 op1 + 0FFh + c op1 ~op1 op1 ~op1 + 1 op1 ~op1 + c - c,z,v,n c,z,n c,z,n c,z,n c,z,n c,z,n c,z,n c,z,n c,z,v,n c,z,v,n c,z,v,n c,z,v,n z,n c,z,v,n c,z,v,n Function Flag z,n z,n z,n c,z,v,n c,z,v,n c,z,v,n c,z,v,n c,z,v,n c,z,v,n z,n z z z z - - z,n - # of word/cycle 1W1C
7-9
INSTRUCTION SET
S3CK318/FK318
QUICK REFERENCE (Continued)
Operation LD LD LD op1 GPR :bank SPR0 GPR op2 GPR :bank #imm:8 GPR SPR adr:8 @idm #imm:8 TBH/TBL GPR GPR GPR - #imm:8 - SPR - op1 op2 op1 op2 op1 op2 Function Flag z,n - z,n # of word / cycle 1W1C
LD LD LD LDC AND OR BANK SWAP LCALL cc
SPR TBH/TBL adr:8 @idm @IL @IL+ SR0 #imm:2 GPR imm:20
op1 op2 op1 op2 op1 op2 (TBH:TBL) PM[(ILX:ILH:ILL)], ILL++ if @IL+ SR0 SR0 & op2 SR0 SR0 | op2 SR0[4:3] op2 op1 op2, op2 op1 (excluding SR0/SR1) If branch taken, push XSTACK, HS[15:0] {PC[15:12],PC[11:0] + 2} and PC op1 else PC[11:0] PC[11:0] + 2 If branch taken, IL[19:0] {PC[19:12], PC[11:0] + 2} and PC op1 else PC[11:0] PC[11:0] + 2 push XSTACK, HS[15:0] {PC[15:12], PC[11:0] + 1} and PC[11:0] op1 IL[19:0] {PC[19:12], PC[11:0] + 1} and PC[11:0] op1 if (Rn == 0) PC PC[delay slot] - 2's complement of imm:8, Rn-else PC PC[delay slot]++, Rn-If branch taken, PC op1 else PC[11:0] < PC[11:0] + 2 If branch taken, PC[11:0] PC[11:0] + op1 else PC[11:0] PC[11:0] + 1
- - - - - - - - 2W2C 1W2C 1W1C
LLNK cc
imm:20
-
-
CALLS LNKS JNZD
imm:12 imm:12 Rn
- - imm:8
- - -
1W2C
LJP cc JR cc
NOTE:
imm:20 imm:9
- -
- -
2W2C 1W2C
op1 - operand1, op2 - operand2, 1W1C - 1-Word 1-Cycle instruction, 1W2C - 1-Word 2-Cycle instruction, 2W2C 2-Word 2-Cycle instruction. The Rn of instruction JNZD is Bank 3's GPR.
7-10
S3CK318/FK318
INSTRUCTION SET
QUICK REFERENCE (Concluded)
Operation LRET RET IRET NOP BREAK SYS CLD CLD COP #imm:8 imm:8 GPR #imm:12 - GPR imm:8 - op1 - op2 - PC IL[19:0] PC HS[sptr - 2], (sptr sptr - 2) PC HS[sptr - 2], (sptr sptr - 2) no operation no operation and hold PC no operation but generates SYSCP[7:0] and nSYSID op1 op2, generates SYSCP[7:0], nCLDID, and CLDWR op1 op2, generates SYSCP[7:0], nCLDID, and CLDWR generates SYSCP[11:0] and nCOPID - - z,n - Function Flag - # of word / cycle 1W2C 1W2C 1W2C 1W1C 1W1C 1W1C
NOTES: 1. op1 - operand1, op2 - operand2, sptr - stack pointer register, 1W1C - 1-Word 1-Cycle instruction, 1W2C - 1-Word 2-Cycle instruction 2. Pseudo instructions -- SCF/RCF Carry flag set or reset instruction -- STOP/IDLE MCU power saving instructions -- EI/DI Exception enable and disable instructions -- JP/LNK/CALL If JR/LNKS/CALLS commands (1 word instructions) can access the target address, there is no conditional code in the case of CALL/LNK, and the JP/LNK/CALL commands are assembled to JR/LNKS/CALLS in linking time, or else the JP/LNK/CALL commands are assembled to LJP/LLNK/LCALL (2 word instructions) instructions.
7-11
INSTRUCTION SET
S3CK318/FK318
INSTRUCTION GROUP SUMMARY
ALU INSTRUCTIONS "ALU instructions" refer to the operations that use ALU to generate results. ALU instructions update the values in Status Register 1 (SR1), namely carry (C), zero (Z), overflow (V), and negative (N), depending on the operation type and the result. ALUop GPR, adr:8 Performs an ALU operation on the value in GPR and the value in DM[adr:8] and stores the result into GPR. ALUop = ADD, SUB, CP, AND, OR, XOR For SUB and CP, GPR+(not DM[adr:8])+1 is performed. adr:8 is the offset in a specific data memory page. The data memory page is 0 or the value of IDH (Index of Data Memory Higher Byte Register), depending on the value of eid in Status Register 0 (SR0). Operation GPR GPR ALUop DM[00h:adr:8] if eid = 0 GPR GPR ALUop DM[IDH:adr8] if eid = 1 Note that this is an 7-bit operation. Example ADD R0, 80h // Assume eid = 1 and IDH = 01H // R0 R0 + DM[0180h]
ALUop GPR, #imm:8 Stores the result of an ALU operation on GPR and an 7-bit immediate value into GPR. ALUop = ADD, SUB, CP, AND, OR, XOR For SUB and CP, GPR+(not #imm:8)+1 is performed. #imm:8 is an 7-bit immediate value. Operation GPR GPR ALUop #imm:8 Example ADD R0, #7Ah // R0 R0 + 7Ah
7-12
S3CK318/FK318
INSTRUCTION SET
ALUop GPRd, GPRs Store the result of ALUop on GPRs and GPRd into GPRd. ALUop = ADD, SUB, CP, AND, OR, XOR For SUB and CP, GPRd + (not GPRs) + 1 is performed. GPRs and GPRd need not be distinct. Operation GPRd GPRd ALUop GPRs GPRd - GPRs when ALUop = CP (comparison only) Example ADD R0, R1 ALUop GPR, @idm Performs ALUop on the value in GPR and DM[ID] and stores the result into GPR. Index register ID is IDH:IDL (IDH:IDL0 or IDH:IDL1). ALUop = ADD, SUB, CP, AND, OR, XOR For SUB and CP, GPR+(not DM[idm])+1 is performed. idm = IDx+off:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) Operation GPR - DM[idm] when ALUop = CP (comparison only) GPR GPR ALUop DM[IDx], IDx IDx + offset:5 when idm = IDx + offset:5 GPR GPR ALUop DM[IDx - offset:5], IDx IDx - offset:5 when idm = [IDx - offset:5] GPR GPR ALUop DM[IDx + offset:5] when idm = [IDx + offset:5]! GPR GPR ALUop DM[IDx - offset:5] when idm = [IDx - offset:5]! When carry is generated from IDL (on a post-increment or pre-decrement), it is propagated to IDH. Example ADD R0, @ID0+2 ADD R0, @[ID0-2] ADD R0, @[ID1+2]! ADD R0, @[ID1-2]! // assume ID0 = 02FFh // R0 R0 + DM[02FFh], IDH 03h and IDL0 01h // assume ID0 = 0201h // R0 R0 + DM[01FFh], IDH 01h and IDL0 FFh // assume ID1 = 02FFh // R0 R0 + DM[0301], IDH 02h and IDL1 FFh // assume ID1 = 0200h // R0 R0 + DM[01FEh], IDH 02h and IDL1 00h // R0 R0 + R1
7-13
INSTRUCTION SET
S3CK318/FK318
ALUopc GPRd, GPRs Performs ALUop with carry on GPRd and GPRs and stores the result into GPRd. ALUopc = ADC, SBC, CPC GPRd and GPRs need not be distinct. Operation GPRd GPRd + GPRs + C when ALUopc = ADC GPRd GPRd + (not GPRs) + C when ALUopc = SBC GPRd + (not GPRs) + C when ALUopc = CPC (comparison only) Example ADD R0, R2 ADC R1, R3 SUB R0, R2 SBC R1, R3 CP R0, R2 CPC R1, R3 ALUopc GPR, adr:8 Performs ALUop with carry on GPR and DM[adr:8]. Operation GPR GPR + DM[adr:8] + C when ALUopc = ADC GPR GPR + (not DM[adr:8]) + C when ALUopc = SBC GPR + (not DM[adr:8]) + C when ALUopc = CPC (comparison only) CPLop GPR (Complement Operations) CPLop = COM, COM2, COMC Operation COM GPR COM2 GPR COMC GPR Example COM2 R0 COMC R1 // assume R1:R0 is a 16-bit signed number. // COM2 and COMC can be used to get the 2's complement of it. not GPR (logical complement) not GPR + 1 (2's complement of GPR) not GPR + C (logical complement of GPR with carry) // assume R1:R0 and R3:R2 are 16-bit signed or unsigned numbers. // to add two 16-bit numbers, use ADD and ADC. // assume R1:R0 and R3:R2 are 16-bit signed or unsigned numbers. // to subtract two 16-bit numbers, use SUB and SBC. // assume both R1:R0 and R3:R2 are 16-bit unsigned numbers. // to compare two 16-bit unsigned numbers, use CP and CPC.
7-14
S3CK318/FK318
INSTRUCTION SET
IncDec GPR (Increment/Decrement Operations) IncDec = INC, INCC, DEC, DECC Operation INC GPR INCC GPR DEC GPR DECC GPR Example INC R0 INCC R1 DEC R0 DECC R1 // assume R1:R0 is a 16-bit number // to increase R1:R0, use INC and INCC. // assume R1:R0 is a 16-bit number // to decrease R1:R0, use DEC and DECC. Increase GPR, i.e., GPR GPR + 1 Increase GPR if carry = 1, i.e., GPR GPR + C Decrease GPR, i.e., GPR GPR + FFh Decrease GPR if carry = 0, i.e., GPR GPR + FFh + C
7-15
INSTRUCTION SET
S3CK318/FK318
SHIFT/ROTATE INSTRUCTIONS Shift (Rotate) instructions shift (rotate) the given operand by 1 bit. Depending on the operation performed, a number of Status Register 1 (SR1) bits, namely Carry (C), Zero (Z), Overflow (V), and Negative (N), are set. SL GPR Operation
7 C GPR 0 0
Carry (C) is the MSB of GPR before shifting, Negative (N) is the MSB of GPR after shifting. Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0. SLA GPR Operation
7 C GPR 0 0
Carry (C) is the MSB of GPR before shifting, Negative (N) is the MSB of GPR after shifting. Overflow (V) will be 1 if the MSB of the result is different from C. Z will be 1 if the result is 0. RL GPR Operation
7 C GPR 0
Carry (C) is the MSB of GPR before rotating. Negative (N) is the MSB of GPR after rotating. Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0. RLC GPR Operation
7 0
GPR C
Carry (C) is the MSB of GPR before rotating, Negative (N) is the MSB of GPR after rotating. Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0.
7-16
S3CK318/FK318
INSTRUCTION SET
SR GPR Operation
7 0 GPR 0 C
Carry (C) is the LSB of GPR before shifting, Negative (N) is the MSB of GPR after shifting. Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0. SRA GPR Operation
7 GPR 0 C
Carry (C) is the LSB of GPR before shifting, Negative (N) is the MSB of GPR after shifting. Overflow (V) is not affected. Z will be 1 if the result is 0. RR GPR Operation
7 GPR 0 C
Carry (C) is the LSB of GPR before rotating. Negative (N) is the MSB of GPR after rotating. Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0. RRC GPR Operation
7 0
GPR C
Carry (C) is the LSB of GPR before rotating, Negative (N) is the MSB of GPR after rotating. Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0.
7-17
INSTRUCTION SET
S3CK318/FK318
LOAD INSTRUCTIONS Load instructions transfer data from data memory to a register or from a register to data memory, or assigns an immediate value into a register. As a side effect, a load instruction placing a value into a register sets the Zero (Z) and Negative (N) bits in Status Register 1 (SR1), if the placed data is 00h and the MSB of the data is 1, respectively. LD GPR, adr:8 Loads the value of DM[adr:8] into GPR. Adr:8 is offset in the page specified by the value of eid in Status Register 0 (SR0). Operation GPR DM[00h:adr:8] if eid = 0 GPR DM[IDH:adr:8] if eid = 1 Note that this is an 7-bit operation. Example LD R0, 80h // assume eid = 1 and IDH= 01H // R0 DM[0180h]
LD GPR, @idm Loads a value from the data memory location specified by @idm into GPR. idm = IDx+off:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) Operation GPR GPR GPR GPR DM[IDx], IDx IDx + offset:5 when idm = IDx + offset:5 DM[IDx - offset:5], IDx IDx - offset:5 when idm = [IDx - offset:5] DM[IDx + offset:5] when idm = [IDx + offset:5]! DM[IDx - offset:5] when idm = [IDx - offset:5]!
When carry is generated from IDL (on a post-increment or pre-decrement), it is propagated to IDH. Example LD R0, @[ID0 + 03h]! // assume IDH:IDL0 = 0270h // R0 DM[0273h], IDH:IDL0 0270h
7-18
S3CK318/FK318
INSTRUCTION SET
LD REG, #imm:8 Loads an 7-bit immediate value into REG. REG can be either GPR or an SPR0 group register - IDH (Index of Data Memory Higher Byte Register), IDL0 (Index of Data Memory Lower Byte Register)/ IDL1, and Status Register 0 (SR0). #imm:8 is an 7-bit immediate value. Operation REG #imm:8 Example LD R0 #7Ah LD IDH, #03h LD GPR:bs:2, GPR:bs:2 Loads a value of a register from a specified bank into another register in a specified bank. Example LD R0:1, R2:3 LD GPR, TBH/TBL Loads the value of TBH or TBL into GPR. TBH and TBL are 7-bit long registers used exclusively for LDC instructions that access program memory. Therefore, after an LDC instruction, LD GPR, TBH/TBL instruction will usually move the data into GPRs, to be used for other operations. Operation GPR TBH (or TBL) Example LDC @IL LD R0, TBH LD R1, TBL LD TBH/TBL, GPR Loads the value of GPR into TBH or TBL. These instructions are used in pair in interrupt service routines to save and restore the values in TBH/TBL as needed. Operation TBH (or TBL) GPR LD GPR, SPR Loads the value of SPR into GPR. Operation GPR SPR Example LD R0, IDH // R0 IDH // gets a program memory item residing @ ILX:ILH:ILL // R0 in bank 1, R2 in bank 3 // R0 7Ah // IDH 03h
7-19
INSTRUCTION SET
S3CK318/FK318
LD SPR, GPR Loads the value of GPR into SPR. Operation SPR GPR Example LD IDH, R0 LD adr:8, GPR Stores the value of GPR into data memory (DM). adr:8 is offset in the page specified by the value of eid in Status Register 0 (SR0). Operation DM[00h:adr:8] GPR if eid = 0 DM[IDH:adr:8] GPR if eid = 1 Note that this is an 7-bit operation. Example LD 7Ah, R0 // assume eid = 1 and IDH = 02h. // DM[027Ah] R0 // IDH R0
LD @idm, GPR Loads a value into the data memory location specified by @idm from GPR. idm = IDx+off:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) Operation DM[IDx] GPR, IDx IDx + offset:5 when idm = IDx + offset:5 DM[IDx - offset:5] GPR, IDx IDx - offset:5 when idm = [IDx - offset:5] DM[IDx + offset:5] GPR when idm = [IDx + offset:5]! DM[IDx - offset:5] GPR when idm = [IDx - offset:5]! When carry is generated from IDL (on a post-increment or pre-decrement), it is propagated to IDH. Example LD @[ID0 + 03h]!, R0 // assume IDH:IDL0 = 0170h // DM[0173h] R0, IDH:IDL0 0170h
7-20
S3CK318/FK318
INSTRUCTION SET
BRANCH INSTRUCTIONS Branch instructions can be categorized into jump instruction, link instruction, and call instruction. A jump instruction does not save the current PC, whereas a call instruction saves ("pushes") the current PC onto the stack and a link instruction saves the PC in the link register IL. Status registers are not affected. Each instruction type has a 2-word format that supports a 20-bit long jump. JR cc:4, imm:9 imm:9 is a signed number (2's complement), an offset to be added to the current PC to compute the target (PC[19:12]:(PC[11:0] + imm:9)). Operation PC[11:0] PC[11:0] + imm:9 PC[11:0] PC[11:0] + 1 Example L18411: JR Z, 107h LJP cc:4, imm:20 Jumps to the program address specified by imm:20. If program size is less than 64K word, PC[19:16] is not affected. Operation PC[15:0] imm[15:0] if branch taken and program size is less than 64K word PC[19:0] imm[19:0] if branch taken and program size is equal to 64K word or more PC [11:0] PC[11:0] + 1 otherwise Example L18411: LJP Z, 10107h JNZD Rn, imm:8 Jumps to the program address specified by imm:8 if the value of the bank 3 register Rn is not zero. JNZD performs only backward jumps, with the value of Rn automatically decreased. There is one delay slot following the JNZD instruction that is always executed, regardless of whether JNZD is taken or not. Operation If (Rn == 0) PC PC[delay slot] (-) 2's complement of imm:8, Rn Rn - 1 else PC PC[delay slot] + 1, Rn Rn - 1. // assume current PC = 18411h. // next instruction's PC is 10107h If Zero (Z) bit is set // assume current PC = 18411h. // next PC is 18518 (18411h + 107h) if Zero (Z) bit is set. if branch taken (i.e., cc:4 resolves to be true) otherwise
7-21
INSTRUCTION SET
S3CK318/FK318
Example LOOP_A:
* * *
// start of loop body
JNZD R0, LOOP_A ADD R1, #2 CALLS imm:12
// jump back to LOOP_A if R0 is not zero // delay slot, always executed (you must use one cycle instruction only)
Saves the current PC on the stack ("pushes" PC) and jumps to the program address specified by imm:12. The current page number PC[19:12] is not changed. Since this is a 1-word instruction, the return address pushed onto the stack is (PC + 1). If nP64KW is low when PC is saved, PC[19:16] is not saved in the stack. Operation HS[sptr][15:0] current PC + 1 and sptr sptr + 2 (push stack) HS[sptr][19:0] current PC + 1 and sptr sptr + 2 (push stack) PC[11:0] imm:12 Example L18411: CALLS 107h // assume current PC = 18411h. // call the subroutine at 18107h, with the current PC pushed // onto the stack (HS 18412h) if nP64KW = 1. if nP64KW = 0 if nP64KW = 1
LCALL cc:4, imm:20 Saves the current PC onto the stack (pushes PC) and jumps to the program address specified by imm:20. Since this is a 2-word instruction, the return address saved in the stack is (PC + 2). If nP64KW, a core input signal is low when PC is saved, 0000111111PC[19:16] is not saved in the stack and PC[19:16] is not set to imm[19:16]. Operation HS[sptr][15:0] current PC + 2 and sptr + 2 (push stack) if branch taken and nP64KW = 0 HS[sptr][19:0] current PC + 2 and sptr + 2 (push stack) if branch taken and nP64KW = 1 PC[15:0] imm[15:0] if branch taken and nP64KW = 0 PC[19:0] imm[19:0] if branch taken and nP64KW = 1 PC[11:0] PC[11:0] + 2 otherwise Example L18411: LCALL NZ, 10107h // assume current PC = 18411h. // call the subroutine at 10107h with the current PC pushed // onto the stack (HS 18413h)
7-22
S3CK318/FK318
INSTRUCTION SET
LNKS imm:12 Saves the current PC in IL and jumps to the program address specified by imm:12. The current page number PC[19:12] is not changed. Since this is a 1-word instruction, the return address saved in IL is (PC + 1). If the program size is less than 64K word when PC is saved, PC[19:16] is not saved in ILX. Operation IL[15:0] current PC + 1 IL[19:0] current PC + 1 PC[11:0] imm:12 Example L18411: LNKS 107h // assume current PC = 18411h. // call the subroutine at 18107h, with the current PC saved // in IL (IL[19:0] 18412h) if program size is 64K word or more. if program size is less than 64K word if program size is equal to 64K word or more
LLNK cc:4, imm:20 Saves the current PC in IL and jumps to the program address specified by imm:20. Since this is a 2-word instruction, the return address saved in IL is (PC + 2). If the program size is less than 64K word when PC is saved, PC[19:16] is not saved in ILX. Operation IL[15:0] current PC + 2 if branch taken and program size is less than 64K word IL[19:0] current PC + 2 if branch taken and program size is 64K word or more PC[15:0] imm[15:0] if branch taken and program size is less than 64K word PC[19:0] imm[19:0] if branch taken and program size is 64K word or more PC[11:0] PC[11:0] + 2 otherwise Example L18411: LLNK NZ, 10107h // assume current PC = 18411h. // call the subroutine at 10107h with the current PC saved // in IL (IL[19:0] 18413h) if program size is 64K word or more
RET, IRET Returns from the current subroutine. IRET sets ie (SR0[1]) in addition. If the program size is less than 64K word, PC[19:16] is not loaded from HS[19:16]. Operation PC[15:0] HS[sptr - 2] and sptr sptr - 2 (pop stack) if program size is less than 64K word PC[19:0] HS[sptr - 2] and sptr sptr - 2 (pop stack) if program size is 64K word or more Example RET // assume sptr = 3h and HS[1] = 18407h. // the next PC will be 18407h and sptr is set to 1h
7-23
INSTRUCTION SET
S3CK318/FK318
LRET Returns from the current subroutine, using the link register IL. If the program size is less than 64K word, PC[19:16] is not loaded from ILX. Operation PC[15:0] IL[15:0] PC[19:0] IL[19:0] Example LRET // assume IL = 18407h. // the next instruction to execute is at PC = 18407h // if program size is 64K word or more if program size is less than 64K word if program size is 64K word or more
JP/LNK/CALL JP/LNK/CALL instructions are pseudo instructions. If JR/LNKS/CALLS commands (1 word instructions) can access the target address, there is no conditional code in the case of CALL/LNK and the JP/LNK/CALL commands are assembled to JR/LNKS/CALLS in linking time or else the JP/LNK/CALL commands are assembled to LJP/LLNK/LCALL (2 word instructions) instructions.
7-24
S3CK318/FK318
INSTRUCTION SET
BIT MANIPULATION INSTRUCTIONS BITop adr:8.bs Performs a bit operation specified by op on the value in the data memory pointed by adr:8 and stores the result into R3 of current GPR bank or back into memory depending on the value of TF bit. BITop = BITS, BITR, BITC, BITT BITS: bit set BITR: bit reset BITC: bit complement BITT: bit test (R3 is not touched in this case) bs: bit location specifier, 0 - 7. Operation R3 DM[00h:adr:8] BITop bs if eid = 0 R3 DM[IDH:adr:8] BITop bs if eid = 1 (no register transfer for BITT) Set the Zero (Z) bit if the result is 0. Example BITS 25h.3 BITT 25h.3 BMC/BMS Clears or sets the TF bit, which is used to determine the destination of BITop instructions. When TF bit is clear, the result of BITop instructions will be stored into R3 (fixed); if the TF bit is set, the result will be written back to memory. Operation TF 0 TF 1 TM GPR, #imm:8 Performs AND operation on GPR and imm:8 and sets the Zero (Z) and Negative (N) bits. No change in GPR. Operation Z, N flag GPR & #imm:8 BITop GPR.bs Performs a bit operation on GPR and stores the result in GPR. Since the equivalent functionality can be achieved using OR GPR, #imm:8, AND GPR, #imm:8, and XOR GPR, #imm:8, this instruction type doesn't have separate op codes. (BMC) (BMS) // assume eid = 0. set bit 3 of DM[00h:25h] and store the result in R3. // check bit 3 of DM[00h:25h] if eid = 0.
7-25
INSTRUCTION SET
S3CK318/FK318
AND SR0, #imm:8/OR SR0, #imm:8 Sets/resets bits in SR0 and stores the result back into SR0. Operation SR0 SR0 & #imm:8 SR0 SR0 | #imm:8 BANK #imm:2 Loads SR0[4:3] with #imm[1:0]. Operation SR0[4:3] #imm[1:0]
MISCELLANEOUS INSTRUCTION SWAP GPR, SPR Swaps the values in GPR and SPR. SR0 and SR1 can NOT be used for this instruction. No flag is updated, even though the destination is GPR. Operation temp SPR SPR GPR GPR temp Example SWAP R0, IDH // assume IDH = 00h and R0 = 08h. // after this, IDH = 08h and R0 = 00h.
PUSH REG Saves REG in the stack (Pushes REG into stack). REG = GPR, SPR Operation HS[sptr][7:0] REG and sptr sptr + 1 Example PUSH R0 // assume R0 = 08h and sptr = 2h // then HS[2][7:0] 08h and sptr 3h
7-26
S3CK318/FK318
INSTRUCTION SET
POP REG Pops stack into REG. REG = GPR, SPR Operation REG HS[sptr-1][7:0] and sptr sptr - 1 Example POP R0 // assume sptr = 3h and HS[2] = 18407h // R0 07h and sptr 2h
POP Pops 2 bytes from the stack and discards the popped data. NOP Does no work but increase PC by 1. BREAK Does nothing and does NOT increment PC. This instruction is for the debugger only. When this instruction is executed, the processor is locked since PC is not incremented. Therefore, this instruction should not be used under any mode other than the debug mode. SYS #imm:8 Does nothing but increase PC by 1 and generates SYSCP[7:0] and nSYSID signals. CLD GPR, imm:8 GPR (imm:8) and generates SYSCP[7:0], nCLDID, and nCLDWR signals. CLD imm:8, GPR (imm:8) GPR and generates SYSCP[7:0], nCLDID, and nCLDWR signals. COP #imm:12 Generates SYSCP[11:0] and nCOPID signals.
7-27
INSTRUCTION SET
S3CK318/FK318
LDC Loads program memory item into register. Operation [TBH:TBL] PM[ILX:ILH:ILL] [TBH:TBL] PM[ILX:ILH:ILL], ILL++ (LDC @IL) (LDC @IL+)
TBH and TBL are temporary registers to hold the transferred program memory items. These can be accessed only by LD GPR and TBL/TBH instruction. Example LD ILX, R1 LD ILH, R2 LD ILL, R3 LDC @IL // assume R1:R2:R3 has the program address to access
// get the program data @(ILX:ILH:ILL) into TBH:TBL
7-28
S3CK318/FK318
INSTRUCTION SET
PSEUDO INSTRUCTIONS EI/DI Exceptions enable and disable instruction. Operation SR0 OR SR0,#00000010b SR0 AND SR0,#11111101b (EI) (DI)
Exceptions are enabled or disabled through this instruction. If there is an EI instruction, the SR0.1 is set and reset, when DI instruction. Example DI
* * *
EI SCF/RCF Carry flag set and reset instruction. Operation CP R0,R0 AND R0,R0 (SCF) (RCF)
Carry flag is set or reset through this instruction. If there is an SCF instruction, the SR1.0 is set and reset, when RCF instruction. Example SCF RCF STOP/IDLE MCU power saving instruction. Operation SYS #0Ah SYS #05h (STOP) (IDLE)
The STOP instruction stops the both CPU clock and system clock and causes the microcontroller to enter STOP mode. The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Example STOP(or IDLE) NOP NOP NOP
* * *
7-29
INSTRUCTION SET
S3CK318/FK318
ADC -- Add with Carry
Format: ADC , : GPR : adr:8, GPR + + C ADC adds the values of and and carry (C) and stores the result back into C: Z: V: N: set if carry is generated. Reset if not. set if result is zero. Reset if not. set if overflow is generated. Reset if not. exclusive OR of V and MSB of result.
Operation:
Flags:
. Example:
ADC
R0, 80h
// If eid = 0, R0 R0 + DM[0080h] + C // If eid = 1, R0 R0 + DM[IDH:80h] + C // R0 R0 + R1 + C
ADC ADD ADC
R0, R1 R0, R2 R1, R3
In the last two instructions, assuming that register pair R1:R0 and R3:R2 are 16-bit signed or unsigned numbers. Even if the result of "ADD R0, R2" is not zero, Z flag can be set to '1' if the result of "ADC R1,R3" is zero. Note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit addition, take care of the change of Z flag.
7-30
S3CK318/FK318
INSTRUCTION SET
ADD -- Add
Format: ADD , : GPR : adr:8, #imm:8, GPR, @idm Operation: + ADD adds the values of and and stores the result back into . Flags: C: Z: V: N: set if carry is generated. Reset if not. set if result is zero. Reset if not. set if overflow is generated. Reset if not. exclusive OR of V and MSB of result.
. Example:
Given: IDH:IDL0 = 80FFh, eid = 1 ADD ADD ADD ADD ADD ADD ADD R0, 80h R0, #12h R1, R2 R0, @ID0 + 2 R0, @[ID0 - 3] R0, @[ID0 + 2]! R0, @[ID0 - 2]! // R0 R0 + DM[8080h] // R0 R0 + 12h // R1 R1 + R2 // R0 // R0 // R0 // R0 R0 + DM[80FFh], IDH 81h, IDL0 01h R0 + DM[80FCh], IDH 80h, IDL0 FCh R0 + DM[8101h], IDH 80h, IDL0 FFh R0 + DM[80FDh], IDH 80h, IDL0 FFh
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
7-31
INSTRUCTION SET
S3CK318/FK318
AND -- Bit-wise AND
Format: AND , : GPR : adr:8, #imm:8, GPR, @idm Operation: & AND performs bit-wise AND on the values in and and stores the result in . Flags: Z: set if result is zero. Reset if not. N: set if the MSB of result is 1. Reset if not. Given: IDH:IDL0 = 01FFh, eid = 1 AND AND AND AND AND AND AND R0, 7Ah R1, #40h R0, R1 R1, @ID0 + 3 R1, @[ID0 - 5] R1, @[ID0 + 7]! R1, @[ID0 - 2]! // R0 R0 & DM[017Ah] // R1 R1 & 40h // R0 R0 & R1 // R1 // R1 // R1 // R1 R1 & DM[01FFh], IDH:IDL0 0202h R1 & DM[01FAh], IDH:IDL0 01FAh R1 & DM[0206h], IDH:IDL0 01FFh R1 & DM[01FDh], IDH:IDL0 01FFh
Example:
In the first instruction, if eid bit in SR0 is zero, register R0 has garbage value because data memory DM[0051h-007Fh] are not mapped in S3CB519/S3FB519. In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
7-32
S3CK318/FK318
INSTRUCTION SET
AND SR0 -- Bit-wise AND with SR0
Format: Operation: AND SR0, #imm:8 SR0 SR0 & imm:8 AND SR0 performs the bit-wise AND operation on the value of SR0 and imm:8 and stores the result in SR0. Flags: Example: - Given: SR0 = 11000010b nIE nIE0 nIE1 EQU EQU EQU AND AND ~02h ~40h ~80h SR0, #nIE | nIE0 | nIE1 SR0, #11111101b
In the first example, the statement "AND SR0, #nIE|nIE0|nIE1" clear all of bits of the global interrupt, interrupt 0 and interrupt 1. On the contrary, cleared bits can be set to '1' by instruction "OR SR0, #imm:8". Refer to instruction OR SR0 for more detailed explanation about enabling bit. In the second example, the statement "AND SR0, #11111101b" is equal to instruction DI, which is disabling interrupt globally.
7-33
INSTRUCTION SET
S3CK318/FK318
BANK -- GPR Bank selection
Format: Operation: Flags:
NOTE:
BANK #imm:2 SR0[4:3] imm:2 - For explanation of the CalmRISC banked register file and its usage, please refer to chapter 3.
Example: BANK LD BANK LD #1 R0, #11h #2 R1, #22h // Select register bank 1 // Bank1's R0 11h // Select register bank 2 // Bank2's R1 22h
7-34
S3CK318/FK318
INSTRUCTION SET
BITC -- Bit Complement
Format: BITC adr:8.bs bs: 3-digit bit specifier Operation: R3 ((adr:8) ^ (2**bs)) (adr:8) ((adr:8) ^ (2**bs)) if (TF == 0) if (TF == 1)
BITC complements the specified bit of a value read from memory and stores the result in R3 or back into memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction. Flags:
NOTE:
Z: set if result is zero. Reset if not. Since the destination register R3 is fixed, it is not specified explicitly. Given: IDH = 01, DM[0180h] = FFh, eid = 1 BMC BITC BMS BITC // TF 0 // R3 FEh, DM[0180h] = FFh // TF 1 // DM[0180h] FDh
Example:
80h.0
80h.1
7-35
INSTRUCTION SET
S3CK318/FK318
BITR -- Bit Reset
Format: BITR adr:8.bs bs: 3-digit bit specifier Operation: R3 ((adr:8) & ((11111111)2 - (2**bs))) (adr:8) ((adr:8) & ((11111111)2 - (2**bs))) if (TF == 0) if (TF == 1)
BITR resets the specified bit of a value read from memory and stores the result in R3 or back into memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction. Flags:
NOTE:
Z: set if result is zero. Reset if not. Since the destination register R3 is fixed, it is not specified explicitly. Given: IDH = 01, DM[0180h] = FFh, eid = 1 BMC BITR BMS BITR // TF 0 // R3 FDh, DM[0180h] = FFh // TF 1 // DM[0180h] FBh
Example:
80h.1
80h.2
7-36
S3CK318/FK318
INSTRUCTION SET
BITS -- Bit Set
Format: BITS adr:8.bs bs: 3-digit bit specifier. Operation: R3 ((adr:8) | (2**bs)) (adr:8) ((adr:8) | (2**bs)) if (TF == 0) if (TF == 1)
BITS sets the specified bit of a value read from memory and stores the result in R3 or back into memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction. Flags:
NOTE:
Z: set if result is zero. Reset if not. Since the destination register R3 is fixed, it is not specified explicitly. Given: IDH = 01, DM[0180h] = F0h, eid = 1 BMC BITS BMS BITS // TF 0 // R3 0F2h, DM[0180h] = F0h // TF 1 // DM[0180h] F4h
Example:
80h.1
80h.2
7-37
INSTRUCTION SET
S3CK318/FK318
BITT -- Bit Test
Format: BITT adr:8.bs bs: 3-digit bit specifier. Operation: Z ~((adr:8) & (2**bs)) BITT tests the specified bit of a value read from memory. Flags: Example: Z: set if result is zero. Reset if not. Given: DM[0080h] = F7h, eid = 0 BITT JR
* * *
80h.3 Z, %1
// Z flag is set to '1' // Jump to label %1 because condition is true.
%1
BITS NOP
* * *
80h.3
7-38
S3CK318/FK318
INSTRUCTION SET
BMC/BMS - TF bit clear/set
Format: Operation: BMS/BMC BMC/BMS clears (sets) the TF bit. TF 0 if BMC TF 1 if BMS TF is a single bit flag which determines the destination of bit operations, such as BITC, BITR, and BITS. Flags:
NOTE:
- BMC/BMS are the only instructions that modify the content of the TF bit. // TF 1 81h.1 // TF 0 81h.2 R0, R3
Example: BMS BITS BMC BITR LD
7-39
INSTRUCTION SET
S3CK318/FK318
CALL -- Conditional Subroutine Call (Pseudo Instruction)
Format: CALL cc:4, imm:20 CALL imm:12 If CALLS can access the target address and there is no conditional code (cc:4), CALL command is assembled to CALLS (1-word instruction) in linking time, else the CALL is assembled to LCALL (2-word instruction). // HS[sptr][15:0] current PC + 2, sptr sptr + 2 // 2-word instruction // HS[sptr][15:0] current PC + 1, sptr sptr + 2 // 1-word instruction
Operation:
Example: CALL
* * *
C, Wait
CALL
* * *
0088h
Wait:
NOP NOP NOP NOP NOP RET
// Address at 0088h
7-40
S3CK318/FK318
INSTRUCTION SET
CALLS -- Call Subroutine
Format: Operation: CALLS imm:12 HS[sptr][15:0] current PC + 1, sptr sptr + 2 if the program size is less than 64K word. HS[sptr][19:0] current PC + 1, sptr sptr + 2 if the program size is equal to or over 64K word. PC[11:0] imm:12 CALLS unconditionally calls a subroutine residing at the address specified by imm:12. Flags: Example: CALLS
* * *
-
Wait
Wait:
NOP NOP NOP RET Because this is a 1-word instruction, the saved returning address on stack is (PC + 1).
7-41
INSTRUCTION SET
S3CK318/FK318
CLD -- Load into Coprocessor
Format: CLD imm:8, : GPR Operation: (imm:8) CLD loads the value of into (imm:8), where imm:8 is used to access the external coprocessor's address space. Flags: Example: AH AL BH BL EQU EQU EQU EQU
* * *
-
00h 01h 02h 03h
CLD CLD CLD CLD
AH, R0 AL, R1 BH, R2 BL, R3
// A[15:8] R0 // A[7:0] R1 // B[15:8] R2 // B[7:0] R3
The registers A[15:0] and B[15:0] are Arithmetic Unit (AU) registers of MAC816. Above instructions generate SYSCP[7:0], nCLDID and CLDWR signals to access MAC816.
7-42
S3CK318/FK318
INSTRUCTION SET
CLD -- Load from Coprocessor
Format: CLD , imm:8 : GPR Operation: (imm:8) CLD loads a value from the coprocessor, whose address is specified by imm:8. Flags: Z: set if the loaded value in is zero. Reset if not. N: set if the MSB of the loaded value in is 1. Reset if not.
Example: AH AL BH BL EQU EQU EQU EQU
* * *
00h 01h 02h 03h
CLD CLD CLD CLD
R0, AH R1, AL R2, BH R3, BL
// R0 A[15:8] // R1 A[7:0] // R2 B[15:8] // R3 B[7:0]
The registers A[15:0] and B[15:0] are Arithmetic Unit (AU) registers of MAC816. Above instructions generate SYSCP[7:0], nCLDID and CLDWR signals to access MAC816.
7-43
INSTRUCTION SET
S3CK318/FK318
COM -- 1's or Bit-wise Complement
Format: COM : GPR Operation: ~ COM takes the bit-wise complement operation on and stores the result in . Flags: Z: set if result is zero. Reset if not. N: set if the MSB of result is 1. Reset if not. Given: R1 = 5Ah COM R1 // R1 A5h, N flag is set to '1'
Example:
7-44
S3CK318/FK318
INSTRUCTION SET
COM2 -- 2's Complement
Format: COM2 : GPR Operation: ~ + 1 COM2 computes the 2's complement of and stores the result in . Flags: C: Z: V: N: set if carry is generated. Reset if not. set if result is zero. Reset if not. set if overflow is generated. Reset if not. set if result is negative.
Example:
Given: R0 = 00h, R1 = 5Ah COM2 COM2 R0 R1 // R0 00h, Z and C flags are set to '1'. // R1 A6h, N flag is set to '1'.
7-45
INSTRUCTION SET
S3CK318/FK318
COMC -- Bit-wise Complement with Carry
Format: COMC : GPR Operation: ~ + C COMC takes the bit-wise complement of , adds carry and stores the result in . Flags: C: Z: V: N: set if carry is generated. Reset if not. set if result is zero. Reset if not. set if overflow is generated. Reset if not. set if result is negative. Reset if not.
Example:
If register pair R1:R0 is a 16-bit number, then the 2's complement of R1:R0 can be obtained by COM2 and COMC as following. COM2 COMC R0 R1
Note that Z flag do not exactly reflect result of 16-bit operation. For example, if 16-bit register pair R1: R0 has value of FF01h, then 2's complement of R1: R0 is made of 00FFh by COM2 and COMC. At this time, by instruction COMC, zero (Z) flag is set to '1' as if the result of 2's complement for 16bit number is zero. Therefore when programming 16-bit comparison, take care of the change of Z flag.
7-46
S3CK318/FK318
INSTRUCTION SET
COP -- Coprocessor
Format: Operation: Flags: Example: COP COP #0D01h #0234h // generate 1 word instruction code(FD01h) // generate 1 word instruction code(F234h) COP #imm:12 COP passes imm:12 to the coprocessor by generating SYSCP[11:0] and nCOPID signals. -
The above two instructions are equal to statement "ELD A, #1234h" for MAC816 operation. The microcode of MAC instruction "ELD A, #1234h" is "FD01F234", 2-word instruction. In this, code "F" indicates "COP" instruction.
7-47
INSTRUCTION SET
S3CK318/FK318
CP -- Compare
Format: CP , : GPR : adr:8, #imm:8, GPR, @idm Operation: + ~ + 1 CP compares the values of and by subtracting from . Contents of and are not changed. Flags: C: Z: V: N: set if carry is generated. Reset if not. set if result is zero (i.e., and are same). Reset if not. set if overflow is generated. Reset if not. set if result is negative. Reset if not.
Example:
Given: R0 = 73h, R1 = A5h, IDH:IDL0 = 0123h, DM[0123h] = A5, eid = 1 CP CP CP CP CP CP CP R0, 80h R0, #73h R0, R1 R1, @ID0 R1, @[ID0 - 5] R2, @[ID0 + 7]! R2, @[ID0 - 2]! // C flag is set to '1' // Z and C flags are set to '1' // V flag is set to '1' // Z and C flags are set to '1'
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
7-48
S3CK318/FK318
INSTRUCTION SET
CPC -- Compare with Carry
Format: CPC , : GPR : adr:8, GPR Operation: + ~ + C CPC compares and by subtracting from . Unlike CP, however, CPC adds (C - 1) to the result. Contents of and are not changed. Flags: C: Z: V: N: set if carry is generated. Reset if not. set if result is zero. Reset if not. set if overflow is generated. Reset if not. set if result is negative. Reset if not.
Example:
If register pair R1:R0 and R3:R2 are 16-bit signed or unsigned numbers, then use CP and CPC to compare two 16-bit numbers as follows. CP CPC R0, R1 R2, R3
Because CPC considers C when comparing and , CP and CPC can be used in pair to compare 16-bit operands. But note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit comparison, take care of the change of Z flag.
7-49
INSTRUCTION SET
S3CK318/FK318
DEC -- Decrement
Format: DEC : GPR Operation: + 0FFh DEC decrease the value in by adding 0FFh to . Flags: C: Z: V: N: set if carry is generated. Reset if not. set if result is zero. Reset if not. set if overflow is generated. Reset if not. set if result is negative. Reset if not.
Example:
Given: R0 = 80h, R1 = 00h DEC DEC R0 R1 // R0 7Fh, C, V and N flags are set to '1' // R1 FFh, N flags is set to '1'
7-50
S3CK318/FK318
INSTRUCTION SET
DECC -- Decrement with Carry
Format: DECC : GPR Operation: + 0FFh + C DECC decrease the value in when carry is not set. When there is a carry, there is no change in the value of . Flags: C: Z: V: N: set if carry is generated. Reset if not. set if result is zero. Reset if not. set if overflow is generated. Reset if not. set if result is negative. Reset if not.
Example:
If register pair R1:R0 is 16-bit signed or unsigned number, then use DEC and DECC to decrement 16-bit number as follows. DEC DECC R0 R1
Note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit decrement, take care of the change of Z flag.
7-51
INSTRUCTION SET
S3CK318/FK318
DI -- Disable Interrupt (Pseudo Instruction)
Format: Operation: DI Disables interrupt globally. It is same as "AND SR0, #0FDh" . DI instruction sets bit1 (ie: global interrupt enable) of SR0 register to '0' - Given: SR0 = 03h DI // SR0 SR0 & 11111101b
Flags: Example:
DI instruction clears SR0[1] to '0', disabling interrupt processing.
7-52
S3CK318/FK318
INSTRUCTION SET
EI -- Enable Interrupt (Pseudo Instruction)
Format: Operation: EI Enables interrupt globally. It is same as "OR SR0, #02h" . EI instruction sets the bit1 (ie: global interrupt enable) of SR0 register to '1' - Given: SR0 = 01h EI // SR0 SR0 | 00000010b
Flags: Example:
The statement "EI" sets the SR0[1] to '1', enabling all interrupts.
7-53
INSTRUCTION SET
S3CK318/FK318
IDLE -- Idle Operation (Pseudo Instruction)
Format: Operation: IDLE The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt or reset operation. The IDLE instruction is a pseudo instruction. It is assembled as "SYS #05H", and this generates the SYSCP[7-0] signals. Then these signals are decoded and the decoded signals execute the idle operation. -
The next instruction of IDLE instruction is executed, so please use the NOP instruction after the IDLE instruction.
Flags:
NOTE:
Example: IDLE NOP NOP NOP
* * *
The IDLE instruction stops the CPU clock but not the system clock.
7-54
S3CK318/FK318
INSTRUCTION SET
INC -- Increment
Format: INC : GPR Operation: + 1 INC increase the value in . Flags: C: Z: V: N: set if carry is generated. Reset if not. set if result is zero. Reset if not. set if overflow is generated. Reset if not. set if result is negative. Reset if not.
Example:
Given: R0 = 7Fh, R1 = FFh INC INC R0 R1 // R0 80h, V flag is set to '1' // R1 00h, Z and C flags are set to '1'
7-55
INSTRUCTION SET
S3CK318/FK318
INCC -- Increment with Carry
Format: INCC : GPR Operation: + C INCC increase the value of only if there is carry. When there is no carry, the value of is not changed. Flags: C: Z: V: N: set if carry is generated. Reset if not. set if result is zero. Reset if not. set if overflow is generated. Reset if not. exclusive OR of V and MSB of result.
Example:
If register pair R1:R0 is 16-bit signed or unsigned number, then use INC and INCC to increment 16-bit number as following. INC INCC R0 R1
Assume R1:R0 is 0010h, statement "INC R0" increase R0 by one without carry and statement "INCC R1" set zero (Z) flag to '1' as if the result of 16-bit increment is zero. Note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit increment, take care of the change of Z flag.
7-56
S3CK318/FK318
INSTRUCTION SET
IRET -- Return from Interrupt Handling
Format: Operation: IRET PC HS[sptr - 2], sptr sptr - 2 IRET pops the return address (after interrupt handling) from the hardware stack and assigns it to PC. The ie (i.e., SR0[1]) bit is set to allow further interrupt generation. Flags:
NOTE:
- The program size (indicated by the nP64KW signal) determines which portion of PC is updated. When the program size is less than 64K word, only the lower 16 bits of PC are updated (i.e., PC[15:0] HS[sptr - 2]). When the program size is 64K word or more, the action taken is PC[19:0] HS[sptr - 2].
Example: SF_EXCEP: NOP
* * *
// Stack full exception service routine
IRET
7-57
INSTRUCTION SET
S3CK318/FK318
JNZD -- Jump Not Zero with Delay slot
Format: JNZD , imm:8 : GPR (bank 3's GPR only) imm:8 is an signed number Operation: PC PC[delay slot] - 2's complement of imm:8 - 1 JNZD performs a backward PC-relative jump if evaluates to be non-zero. Furthermore, JNZD decrease the value of . The instruction immediately following JNZD (i.e., in delay slot) is always executed, and this instruction must be 1 cycle instruction. Flags:
NOTE:
- Typically, the delay slot will be filled with an instruction from the loop body. It is noted, however, that the chosen instruction should be "dead" outside the loop for it executes even when the loop is exited (i.e., JNZD is not taken). Given: IDH = 03h, eid = 1 BANK LD LD LD JNZD LD
* * *
Example:
%1
#3 R0, #0FFh R1, #0 IDL0, R0 R0, %B1 @ID0, R1
// R0 is used to loop counter
// If R0 of bank3 is not zero, jump to %1. // Clear register pointed by ID0
This example can be used for RAM clear routine. The last instruction is executed even if the loop is exited.
7-58
S3CK318/FK318
INSTRUCTION SET
JP -- Conditional Jump (Pseudo Instruction)
Format: JP cc:4 imm:20 JP cc:4 imm:9 If JR can access the target address, JP command is assembled to JR (1 word instruction) in linking time, else the JP is assembled to LJP (2 word instruction) instruction. There are 16 different conditions that can be used, as described in table 7-6.
Operation:
Example: %1
LD
* * *
R0, #10h
// Assume address of label %1 is 020Dh
JP JP
* * *
Z, %B1 C, %F2
// Address at 0264h // Address at 0265h
%2
LD
* * *
R1, #20h
// Assume address of label %2 is 089Ch
In the above example, the statement "JP Z, %B1" is assembled to JR instruction. Assuming that current PC is 0264h and condition is true, next PC is made by PC[11:0] PC[11:0] + offset, offset value is "64h + A9h" without carry. "A9" means 2's complement of offset value to jump backward. Therefore next PC is 020Dh. On the other hand, statement "JP C, %F2" is assembled to LJP instruction because offset address exceeds the range of imm:9.
7-59
INSTRUCTION SET
S3CK318/FK318
JR -- Conditional Jump Relative
Format: JR cc:4 imm:9 cc:4: 4-bit condition code Operation: PC[11:0] PC[11:0] + imm:9 if condition is true. imm:9 is a signed number, which is signextended to 12 bits when added to PC. There are 16 different conditions that can be used, as described in table 7-6. - Unlike LJP, the target address of JR is PC-relative. In the case of JR, imm:9 is added to PC to compute the actual jump address, while LJP directly jumps to imm:20, the target.
Flags:
NOTE:
Example: JR
* * *
Z, %1
// Assume current PC = 1000h
%1
LD
* * *
R0, R1
// Address at 10A5h
After the first instruction is executed, next PC has become 10A5h if Z flag bit is set to '1'. The range of the relative address is from +255 to -256 because imm:9 is signed number.
7-60
S3CK318/FK318
INSTRUCTION SET
LCALL -- Conditional Subroutine Call
Format: Operation: LCALL cc:4, imm:20 HS[sptr][15:0] current PC + 2, sptr sptr + 2, PC[15:0] imm[15:0] if the condition holds and the program size is less than 64K word. HS[sptr][19:0] current PC + 2, sptr sptr + 2, PC[19:0] imm:20 if the condition holds and the program size is equal to or over 64K word. PC[11:0] PC[11:0] + 2 otherwise. LCALL instruction is used to call a subroutine whose starting address is specified by imm:20. Flags: Example: LCALL LCALL L1 C, L2 -
Label L1 and L2 can be allocated to the same or other section. Because this is a 2-word instruction, the saved returning address on stack is (PC + 2).
7-61
INSTRUCTION SET
S3CK318/FK318
LD adr:8 -- Load into Memory
Format: LD adr:8, : GPR Operation: DM[00h:adr:8] if eid = 0 DM[IDH:adr:8] if eid = 1 LD adr:8 loads the value of into a memory location. The memory location is determined by the eid bit and adr:8. Flags: Example: - Given: IDH = 01h LD 80h, R0
If eid bit of SR0 is zero, the statement "LD 80h, R0" load value of R0 into DM[0080h], else eid bit was set to '1', the statement "LD 80h, R0" load value of R0 into DM[0180h]
7-62
S3CK318/FK318
INSTRUCTION SET
LD @idm -- Load into Memory Indexed
Format: LD @idm, : GPR Operation: (@idm) LD @idm loads the value of into the memory location determined by @idm. Details of the @idm format and how the actual address is calculated can be found in chapter 2. Flags: Example: - Given R0 = 5Ah, IDH:IDL0 = 8023h, eid = 1 LD LD LD LD LD @ID0, R0 @ID0 + 3, R0 @[ID0-5], R0 @[ID0+4]!, R0 @[ID0-2]!, R0 // // // // // DM[8023h] 5Ah DM[8023h] 5Ah, IDL0 26h DM[801Eh] 5Ah, IDL0 1Eh DM[8027h] 5Ah, IDL0 23h DM[8021h] 5Ah, IDL0 23h
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
7-63
INSTRUCTION SET
S3CK318/FK318
LD -- Load Register
Format: LD , : GPR : GPR, SPR, adr:8, @idm, #imm:8 Operation: LD loads a value specified by into the register designated by . Flags: Z: set if result is zero. Reset if not. N: exclusive OR of V and MSB of result. Given: R0 = 5Ah, R1 = AAh, IDH:IDL0 = 8023h, eid = 1 LD LD LD LD LD LD LD LD R0, R1 R1, IDH R2, 80h R0, #11h R0, @ID0+1 R1, @[ID0-2] R2, @[ID0+3]! R3, @[ID0-5]! // R0 AAh // R1 80h // R2 DM[8080h] // R0 11h // R0 // R1 // R2 // R3 DM[8023h], IDL0 24h DM[8021h], IDL0 21h DM[8026h], IDL0 23h DM[801Eh], IDL0 23h
Example:
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
7-64
S3CK318/FK318
INSTRUCTION SET
LD -- Load GPR:bankd, GPR:banks
Format: LD , : GPR: bankd : GPR: banks Operation: LD loads a value of a register in a specified bank (banks) into another register in a specified bank (bankd). Flags: Z: set if result is zero. Reset if not. N: exclusive OR of V and MSB of result. // Bank1's R2 bank3's R0 // Bank0's R0 bank2's R0
Example: LD LD R2:1, R0:3 R0:0, R0:2
7-65
INSTRUCTION SET
S3CK318/FK318
LD -- Load GPR, TBH/TBL
Format: LD , : GPR : TBH/TBL Operation: LD loads a value specified by into the register designated by . Flags: Z: set if result is zero. Reset if not. N: exclusive OR of V and MSB of result. Given: register pair R1:R0 is 16-bit unsigned data. LDC LD LD @IL R1, TBH R0, TBL // TBH:TBL PM[ILX:ILH:ILL] // R1 TBH // R0 TBL
Example:
7-66
S3CK318/FK318
INSTRUCTION SET
LD -- Load TBH/TBL, GPR
Format: LD , : TBH/TBL : GPR Operation: LD loads a value specified by into the register designated by . Flags: Example: - Given: register pair R1:R0 is 16-bit unsigned data. LD LD TBH, R1 TBL, R0 // TBH R1 // TBL R0
7-67
INSTRUCTION SET
S3CK318/FK318
LD SPR
Format:
-- Load SPR
LD , : SPR : GPR
Operation:
LD SPR loads the value of a GPR into an SPR. Refer to Table 3-1 for more detailed explanation about kind of SPR.
Flags: Example:
- Given: register pair R1:R0 = 1020h LD LD ILH, R1 ILL, R0 // ILH 10h // ILL 20h
7-68
S3CK318/FK318
INSTRUCTION SET
LD SPR0 -- Load SPR0 Immediate
Format: Operation: LD SPR0, #imm:8 SPR0 imm:8 LD SPR0 loads an 7-bit immediate value into SPR0. Flags: Example: - Given: eid = 1, idb = 0 (index register bank 0 selection) LD LD LD LD IDH, #80h IDL1, #44h IDL0, #55h SR0, #02h // IDH point to page 80h
The last instruction set ie (global interrupt enable) bit to '1'. Special register group 1 (SPR1) registers are not supported in this addressing mode.
7-69
INSTRUCTION SET
S3CK318/FK318
LDC -- Load Code
Format: LDC : @IL, @IL+ Operation: TBH:TBL PM[ILX:ILH:ILL] ILL ILL + 1 (@IL+ only) LDC loads a data item from program memory and stores it in the TBH:TBL register pair. @IL+ increase the value of ILL, efficiently implementing table lookup operations. Flags: Example: LD LD LD LDC LD LD ILX, R1 ILH, R2 ILL, R3 @IL R1, TBH R0, TBL -
// Loads value of PM[ILX:ILH:ILL] into TBH:TBL // Move data in TBH:TBL to GPRs for further processing
The statement "LDC @IL" do not increase, but if you use statement "LDC @IL+", ILL register is increased by one after instruction execution.
7-70
S3CK318/FK318
INSTRUCTION SET
LJP -- Conditional Jump
Format: LJP cc:4, imm:20 cc:4: 4-bit condition code Operation: PC[15:0] imm[15:0] if condition is true and the program size is less than 64K word. If the program is equal to or larger than 64K word, PC[19:0] imm[19:0] as long as the condition is true. There are 16 different conditions that can be used, as described in table 7-6. - LJP cc:4 imm:20 is a 2-word instruction whose immediate field directly specifies the target address of the jump.
Flags:
NOTE:
Example: LJP
* * *
C, %1
// Assume current PC = 0812h
%1
LD
* * *
R0, R1
// Address at 10A5h
After the first instruction is executed, LJP directly jumps to address 10A5h if condition is true.
7-71
INSTRUCTION SET
S3CK318/FK318
LLNK -- Linked Subroutine Call Conditional
Format: LLNK cc:4, imm:20 cc:4: 4-bit condition code Operation: If condition is true, IL[19:0] {PC[19:12], PC[11:0] + 2}. Further, when the program is equal to or larger than 64K word, PC[19:0] imm[19:0] as long as the condition is true. If the program is smaller than 64K word, PC[15:0] imm[15:0]. There are 16 different conditions that can be used, as described in table 7-6. Flags:
NOTE:
- LLNK is used to conditionally to call a subroutine with the return address saved in the link register (IL) without stack operation. This is a 2-word instruction.
Example: LLNK NOP
* * *
Z, %1
// Address at 005Ch, ILX:ILH:ILL 00:00:5Eh // Address at 005Eh
%1
LD
* * *
R0, R1
LRET
7-72
S3CK318/FK318
INSTRUCTION SET
LNK -- Linked Subroutine Call (Pseudo Instruction)
Format: LNK cc:4, imm:20 LNK imm:12 If LNKS can access the target address and there is no conditional code (cc:4), LNK command is assembled to LNKS (1 word instruction) in linking time, else the LNK is assembled to LLNK (2 word instruction).
Operation:
Example: LNK LNK NOP
* * *
Z, Link1 Link2
// Equal to "LLNK Z, Link1" // Equal to "LNKS Link2"
Link2:
NOP
* * *
LRET Subroutines section CODE, ABS 0A00h Subroutines Link1: NOP
* * *
LRET
7-73
INSTRUCTION SET
S3CK318/FK318
LNKS -- Linked Subroutine Call
Format: Operation: LNKS imm:12 IL[19:0] {PC[19:12], PC[11:0] + 1} and PC[11:0] imm:12 LNKS saves the current PC in the link register and jumps to the address specified by imm:12. - LNKS is used to call a subroutine with the return address saved in the link register (IL) without stack
operation.
Flags:
NOTE:
Example: LNKS NOP
* * *
Link1
// Address at 005Ch, ILX:ILH:ILL 00:00:5Dh // Address at 005Dh
Link1:
NOP
* * *
LRET
7-74
S3CK318/FK318
INSTRUCTION SET
LRET -- Return from Linked Subroutine Call
Format: Operation: LRET PC IL[19:0] LRET returns from a subroutine by assigning the saved return address in IL to PC. -
Flags: Example: Link1:
LNK NOP
* * *
Link1
LRET
; PC[19:0] ILX:ILH:ILL
7-75
INSTRUCTION SET
S3CK318/FK318
NOP -- No Operation
Format: Operation: NOP No operation. When the instruction NOP is executed in a program, no operation occurs. Instead, the instruction time is delayed by approximately one machine cycle per each NOP instruction encountered.
Flags: Example:
-
NOP
7-76
S3CK318/FK318
INSTRUCTION SET
OR -- Bit-wise OR
Format: OR , : GPR : adr:8, #imm:8, GPR, @idm Operation: | OR performs the bit-wise OR operation on and and stores the result in . Z: set if result is zero. Reset if not. N: exclusive OR of V and MSB of result. Given: IDH:IDL0 = 031Eh, eid = 1 OR OR OR OR OR OR OR R0, 80h R1, #40h R1, R0 R0, @ID0 R1, @[ID0-1] R2, @[ID0+1]! R3, @[ID0-1]! // R0 R0 | DM[0380h] // Mask bit6 of R1 // R1 R1 | R0 // R0 // R1 // R2 // R3 R0 | DM[031Eh], IDL0 1Eh R1 | DM[031Dh], IDL0 1Dh R2 | DM[031Fh], IDL0 1Eh R3 | DM[031Dh], IDL0 1Eh
Flags:
Example:
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
7-77
INSTRUCTION SET
S3CK318/FK318
OR SR0 -- Bit-wise OR with SR0
Format: Operation: OR SR0, #imm:8 SR0 SR0 | imm:8 OR SR0 performs the bit-wise OR operation on SR0 and imm:8 and stores the result in SR0. Flags: Example: - Given: SR0 = 00000000b EID IE IDB1 IE0 IE1 EQU EQU EQU EQU EQU OR OR 01h 02h 04h 40h 80h SR0, #IE | IE0 | IE1 SR0, #00000010b
In the first example, the statement "OR SR0, #EID|IE|IE0" set global interrupt(ie), interrupt 0(ie0) and interrupt 1(ie1) to '1' in SR0. On the contrary, enabled bits can be cleared with instruction "AND SR0, #imm:8". Refer to instruction AND SR0 for more detailed explanation about disabling bit. In the second example, the statement "OR SR0, #00000010b" is equal to instruction EI, which is enabling interrupt globally.
7-78
S3CK318/FK318
INSTRUCTION SET
POP -- POP
Format: Operation: POP sptr sptr - 2 POP decrease sptr by 2. The top two bytes of the hardware stack are therefore invalidated. Flags: Example: - Given: sptr[5:0] = 001010b POP This POP instruction decrease sptr[5:0] by 2. Therefore sptr[5:0] is 001000b.
7-79
INSTRUCTION SET
S3CK318/FK318
POP -- POP to Register
Format: POP : GPR, SPR Operation: HS[sptr - 1], sptr sptr - 1 POP copies the value on top of the stack to and decrease sptr by 1. Flags: Z: set if the value copied to is zero. Reset if not. N: set if the value copied to is negative. Reset if not. When is SPR, no flags are affected, including Z and N. // R0 HS[sptr-1], sptr sptr-1 // IDH HS[sptr-1], sptr sptr-1
Example: POP POP R0 IDH
In the first instruction, value of HS[sptr-1] is loaded to R0 and the second instruction "POP IDH" load value of HS[sptr-1] to register IDH. Refer to chapter 5 for more detailed explanation about POP operations for hardware stack.
7-80
S3CK318/FK318
INSTRUCTION SET
PUSH -- Push Register
Format: PUSH : GPR, SPR Operation: HS[sptr] , sptr sptr + 1 PUSH stores the value of on top of the stack and increase sptr by 1. Flags: Example: PUSH PUSH R0 IDH // HS[sptr] R0, sptr sptr + 1 // HS[sptr] IDH, sptr sptr + 1 -
In the first instruction, value of register R0 is loaded to HS[sptr-1] and the second instruction "PUSH IDH" load value of register IDH to HS[sptr-1]. Current HS pointed by stack point sptr[5:0] be emptied. Refer to chapter 5 for more detailed explanation about PUSH operations for hardware stack.
7-81
INSTRUCTION SET
S3CK318/FK318
RET -- Return from Subroutine
Format: Operation: RET PC HS[sptr - 2], sptr sptr - 2 RET pops an address on the hardware stack into PC so that control returns to the subroutine call site. Flags: Example: - Given: sptr[5:0] = 001010b CALLS
* * *
Wait
// Address at 00120h
Wait:
NOP NOP NOP NOP NOP RET
// Address at 01000h
After the first instruction CALLS execution, "PC+1", 0121h is loaded to HS[5] and hardware stack pointer sptr[5:0] have 001100b and next PC became 01000h. The instruction RET pops value 0121h on the hardware stack HS[sptr-2] and load to PC then stack pointer sptr[[5:0] became 001010b.
7-82
S3CK318/FK318
INSTRUCTION SET
RL -- Rotate Left
Format: RL : GPR Operation: C [7], {[6:0], [7]} RL rotates the value of to the left and stores the result back into . The original MSB of is copied into carry (C). Flags: C: set if the MSB of (before rotating) is 1. Reset if not. Z: set if result is zero. Reset if not. N: set if the MSB of (after rotating) is 1. Reset if not. Given: R0 = 01001010b, R1 = 10100101b RL RL R0 R1 // N flag is set to '1', R0 10010100b // C flag is set to '1', R1 01001011b
Example:
7-83
INSTRUCTION SET
S3CK318/FK318
RLC -- Rotate Left with Carry
Format: RLC : GPR Operation: C [7], {[6:0], C} RLC rotates the value of to the left and stores the result back into . The original MSB of is copied into carry (C), and the original C bit is copied into [0]. Flags: C: set if the MSB of (before rotating) is 1. Reset if not. Z: set if result is zero. Reset if not. N: set if the MSB of (after rotating) is 1. Reset if not. Given: R2 = A5h, if C = 0 RLC RL RLC R2 R0 R1 // R2 4Ah, C flag is set to '1'
Example:
In the second example, assuming that register pair R1:R0 is 16-bit number, then RL and RLC are used for 16-bit rotate left operation. But note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit decrement, take care of the change of Z flag.
7-84
S3CK318/FK318
INSTRUCTION SET
RR -- Rotate Right
Format: RR : GPR Operation: C [0], {[0], [7:1]} RR rotates the value of to the right and stores the result back into . The original LSB of is copied into carry (C). Flags: C: set if the LSB of (before rotating) is 1. Reset if not. Z: set if result is zero. Reset if not. N: set if the MSB of (after rotating) is 1. Reset if not. Given: R0 = 01011010b, R1 = 10100101b RR RR R0 R1 // No change of flag, R0 00101101b // C and N flags are set to '1', R1 11010010b
Example:
7-85
INSTRUCTION SET
S3CK318/FK318
RRC -- Rotate Right with Carry
Format: RRC : GPR Operation: C [0], {C, [7:1]} RRC rotates the value of to the right and stores the result back into . The original LSB of is copied into carry (C), and C is copied to the MSB. Flags: C: set if the LSB of (before rotating) is 1. Reset if not. Z: set if result is zero. Reset if not. N: set if the MSB of (after rotating) is 1. Reset if not. Given: R2 = A5h, if C = 0 RRC RR RRC R2 R0 R1 // R2 52h, C flag is set to '1'
Example:
In the second example, assuming that register pair R1:R0 is 16-bit number, then RR and RRC are used for 16-bit rotate right operation. But note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit decrement, take care of the change of Z flag.
7-86
S3CK318/FK318
INSTRUCTION SET
SBC -- Subtract with Carry
Format: SBC , : GPR : adr:8, GPR Operation: + ~ + C SBC computes ( - ) when there is carry and ( - - 1) when there is no carry. Flags: C: Z: V: N: set if carry is generated. Reset if not. set if result is zero. Reset if not. set if overflow is generated. set if result is negative. Reset if not.
Example: SBC R0, 80h // If eid = 0, R0 R0 + ~DM[0080h] + C // If eid = 1, R0 R0 + ~DM[IDH:80h] + C // R0 R0 + ~R1 + C
SBC SUB SBC
R0, R1 R0, R2 R1, R3
In the last two instructions, assuming that register pair R1:R0 and R3:R2 are 16-bit signed or unsigned numbers. Even if the result of "ADD R0, R2" is not zero, zero (Z) flag can be set to '1' if the result of "SBC R1,R3" is zero. Note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit addition, take care of the change of Z flag.
7-87
INSTRUCTION SET
S3CK318/FK318
SL -- Shift Left
Format: SL : GPR Operation: C [7], {[6:0], 0} SL shifts to the left by 1 bit. The MSB of the original is copied into carry (C). Flags: C: set if the MSB of (before shifting) is 1. Reset if not. Z: set if result is zero. Reset if not. N: set if the MSB of (after shifting) is 1. Reset if not. Given: R0 = 01001010b, R1 = 10100101b SL SL R0 R1 // N flag is set to '1', R0 10010100b // C flag is set to '1', R1 01001010b
Example:
7-88
S3CK318/FK318
INSTRUCTION SET
SLA -- Shift Left Arithmetic
Format: SLA : GPR Operation: C [7], {[6:0], 0} SLA shifts to the left by 1 bit. The MSB of the original is copied into carry (C). Flags: C: Z: V: N: set if the MSB of (before shifting) is 1. Reset if not. set if result is zero. Reset if not. set if the MSB of the result is different from C. Reset if not. set if the MSB of (after shifting) is 1. Reset if not.
Example:
Given: R0 = AAh SLA R0 // C, V, N flags are set to '1', R0 54h
7-89
INSTRUCTION SET
S3CK318/FK318
SR -- Shift Right
Format: SR : GPR Operation: C [0], {0, [7:1]} SR shifts to the right by 1 bit. The LSB of the original (i.e., [0]) is copied into carry (C). Flags: C: set if the LSB of (before shifting) is 1. Reset if not. Z: set if result is zero. Reset if not. N: set if the MSB of (after shifting) is 1. Reset if not. Given: R0 = 01011010b, R1 = 10100101b SR SR R0 R1 // No change of flags, R0 00101101b // C flag is set to '1', R1 01010010b
Example:
7-90
S3CK318/FK318
INSTRUCTION SET
SRA -- Shift Right Arithmetic
Format: SRA : GPR Operation: C [0], {[7], [7:1]} SRA shifts to the right by 1 bit while keeping the sign of . The LSB of the original (i.e., [0]) is copied into carry (C). Flags: C: set if the LSB of (before shifting) is 1. Reset if not. Z: set if result is zero. Reset if not. N: set if the MSB of (after shifting) is 1. Reset if not.
SRA keeps the sign bit or the MSB ([7]) in its original position. If SRA is executed 'N' times, N significant bits will be set, followed by the shifted bits.
NOTE:
Example:
Given: R0 = 10100101b SRA SRA SRA SRA R0 R0 R0 R0 // C, N flags are set to '1', R0 11010010b // N flag is set to '1', R0 11101001b // C, N flags are set to '1', R0 11110100b // N flags are set to '1', R0 11111010b
7-91
INSTRUCTION SET
S3CK318/FK318
STOP -- Stop Operation (pseudo instruction)
Format: Operation: STOP The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter the STOP mode. In the STOP mode, the contents of the on-chip CPU registers, peripheral registers, and I/O port control and data register are retained. A reset operation or external or internal interrupts can release stop mode. The STOP instruction is a pseudo instruction. It is assembled as "SYS #0Ah", which generates the SYSCP[7-0] signals. These signals are decoded and stop the operation. The next instruction of STOP instruction is executed, so please use the NOP instruction after the STOP instruction.
NOTE:
Example: STOP NOP NOP NOP
* * *
In this example, the NOP instructions provide the necessary timing delay for oscillation stabilization before the next instruction in the program sequence is executed. Refer to the timing diagrams of oscillation stabilization, as described in Figure 21-4, 21-5.
7-92
S3CK318/FK318
INSTRUCTION SET
SUB -- Subtract
Format: SUB , : GPR : adr:8, #imm:8, GPR, @idm Operation: + ~ + 1 SUB adds the value of with the 2's complement of to perform subtraction on and Flags: C: Z: V: N: set if carry is generated. Reset if not. set if result is zero. Reset if not. set if overflow is generated. Reset if not. set if result is negative. Reset if not.
Example:
Given: IDH:IDL0 = 0150h, DM[0143h] = 26h, R0 = 52h, R1 = 14h, eid = 1 SUB SUB SUB SUB SUB SUB SUB R0, 43h R1, #16h R0, R1 R0, @ID0+1 R0, @[ID0-2] R0, @[ID0+3]! R0, @[ID0-2]! // R0 R0 + ~DM[0143h] + 1 = 2Ch // R1 FEh, N flag is set to '1' // R0 R0 + ~R1 + 1 = 3Eh // R0 // R0 // R0 // R0 R0 + ~DM[0150h] + 1, IDL0 51h R0 + ~DM[014Eh] + 1, IDL0 4Eh R0 + ~DM[0153h] + 1, IDL0 50h R0 + ~DM[014Eh] + 1, IDL0 50h
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed explanation about this addressing mode. The example in the SBC description shows how SUB and SBC can be used in pair to subtract a 16-bit number from another. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
7-93
INSTRUCTION SET
S3CK318/FK318
SWAP -- Swap
Format: SWAP , : GPR : SPR Operation: , SWAP swaps the values of the two operands. Flags:
NOTE:
- Among the SPRs, SR0 and SR1 can not be used as . Given: IDH:IDL0 = 8023h, R0 = 56h, R1 = 01h SWAP SWAP R1, IDH R0, IDL0 // R1 80h, IDH 01h // R0 23h, IDL0 56h
Example:
After execution of instructions, index registers IDH:IDL0 (ID0) have address 0156h.
7-94
S3CK318/FK318
INSTRUCTION SET
SYS -- System
Format: Operation: Flags:
NOTE:
SYS #imm:8 SYS generates SYSCP[7:0] and nSYSID signals. - Mainly used for system peripheral interfacing.
Example: SYS SYS #0Ah #05h
In the first example, statement "SYS #0Ah" is equal to STOP instruction and second example "SYS #05h" is equal to IDLE instruction. This instruction does nothing but increase PC by one and generates SYSCP[7:0] and nSYSID signals.
7-95
INSTRUCTION SET
S3CK318/FK318
TM -- Test Multiple Bits
Format: TM , #imm:8 : GPR Operation: TM performs the bit-wise AND operation on and imm:8 and sets the flags. The content of is not changed. Z: set if result is zero. Reset if not. N: set if result is negative. Reset if not. Given: R0 = 01001101b TM R0, #00100010b // Z flag is set to '1'
Flags:
Example:
7-96
S3CK318/FK318
INSTRUCTION SET
XOR -- Exclusive OR
Format: XOR , : GPR : adr:8, #imm:8, GPR, @idm Operation: ^ XOR performs the bit-wise exclusive-OR operation on and and stores the result in . Flags: Example: Z: set if result is zero. Reset if not. N: set if result is negative. Reset if not. Given: IDH:IDL0 = 8080h, DM[8043h] = 26h, R0 = 52h, R1 = 14h, eid = 1 XOR XOR XOR XOR XOR XOR XOR R0, 43h R1, #00101100b R0, R1 R0, @ID0 R0, @[ID0-2] R0, @[ID0+3]! R0, @[ID0-5]! // R0 74h // R1 38h // R0 46h // R0 // R0 // R0 // R0 R0 ^ DM[8080h], IDL0 81h R0 ^ DM[807Eh], IDL0 7Eh R0 ^ DM[8083h], IDL0 80h R0 ^ DM[807Bh], IDL0 80h
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
7-97
INSTRUCTION SET
S3CK318/FK318
NOTES
7-98
S3CK318/FK318
CLOCK CIRCUIT
8
CLOCK CIRCUIT
SYSTEM CLOCK CIRCUIT
The system clock circuit has the following components: -- External crystal, ceramic resonator, or RC oscillation source (or an external clock source) -- Oscillator stop and wake-up functions -- Programmable frequency divider for the CPU clock (fOSC divided by 1, 2, 4, 8, 16, 32, 64, 128) -- System clock control register, PCON -- Oscillator control register, OSCCON
C1
XIN
S3CK318
C2
XOUT
Figure 8-1. Main Oscillator Circuit (Crystal or Ceramic Oscillator)
XIN
S3CK318
XOUT
Figure 8-2. Main Oscillator Circuit (RC Oscillator)
8-1
CLOCK CIRCUIT
S3CK318/FK318
C1
XT IN
S3CK318
C2
XT OUT
Figure 8-3. Sub Oscillator Circuit (Crystal or Ceramic Oscillator)
8-2
S3CK318/FK318
CLOCK CIRCUIT
INT
Stop Release
Stop Release
INT
Main-System Oscillator Circuit
fx
fxt
Sub-System Oscillator Circuit
Watch Timer LCD Controller Frequency Counter
Selector 1 Stop fxx
OSCCON.3 OSCCON.0 1/1 - 1/4096 Frequency Dividing Circuit 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128
Stop
OSCCON.2
Basic Timer, Timer/Counter 0,1 Watch Timer LCD Controller BLD SIO A/D Converter D/A Converter Frequency Counter
PCON.2 - .0
Selector 2 CPU CPU Stop Signal by Idle or Stop
SYS #05H SYS #0AH
Idle Stop
Oscillator Control Circuit
Figure 8-4. System Clock Circuit Diagram
8-3
CLOCK CIRCUIT
S3CK318/FK318
Power Control Register (PCON) 02H, R/W, Reset: 04H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
System clock selection bits: 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fxx/128 fxx/64 fxx/32 fxx/16 fxx/8 fxx/4 fxx/2 fxx/1
Figure 8-5. Power Control Register (PCON)
Oscillator Control Register (OSCCON) 03H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
System clock source selection bit: 0 Main oscillator select 1 Sub oscillator select Not used Sub oscillator control bit: 0 1 Sub oscillator RUN Sub oscillator STOP
Main oscillator control bit: 0 1 Main oscillator RUN Main oscillator STOP
Figure 8-6. Oscillator Control Register (OSCCON)
8-4
S3CK318/FK318
RESET AND POWER-DOWN
9
OVERVIEW
RESET AND POWER-DOWN
During a power-on reset, the voltage at VDD goes to High level and the nRESET pin is forced to Low level. The nRESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings MCU into a known operating status. For the time for CPU clock oscillation to stabilize, the nRESET pin must be held to low level for a minimum time interval after the power supply comes within tolerance. For the minimum time interval, see the electrical characteristics. In summary, the following sequence of events occurs during a reset operation: -- All interrupts are disabled. -- The watchdog function (basic timer) is enabled. -- Ports are set to input mode. -- Peripheral control and data registers are disabled and reset to their default hardware values. -- The program counter (PC) is loaded with the program reset address in the ROM, 00000H. -- When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location 00000H is fetched and executed. NOTE To program the duration of the oscillation stabilization interval, make the appropriate settings to the watchdog timer control register, WDTCON, before entering STOP mode.
9-1
RESET AND POWER-DOWN
S3CK318/FK318
NOTES
9-2
S3CK318/FK318
I/O PORT
10
PORT 0
I/O PORTS
Port 0 Pull-up Control Register (P0PUR) 20H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P0.0/AMF Not used P0 pull-up resistor settings: 0 1 Enable pull-up resistor Disable pull-up resistor P0.1/FMF
Figure 10-1. Port 0 Pull-up Control Register (P0PUR)
10-1
I/O PORT
S3CK318/FK318
PORT 1
Port 1 Control Register (P1CON) 24H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P1.3/ INT3/ BUZ
P1.2/ INT2/ T0CAP
P1.1/ INT1/ T0CLK
P1.0/ INT0/ T0OUT/ T0PWM
P1CON bit-pair pin configuration settings: 0 0 1 1 0 1 0 1 Schmitt trigger input mode (T0CLK, T0CAP) Output mode, open-drain Alternative function (T0OUT/T0PWM, BUZ) Output mode, push-pull
Figure 10-2. Port 1 Control Register (P1CON)
Port 1 Pull-up Control Register (P1PUR) 25H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P1.0 Not used P1.3 P1 pull-up resistor settings: 0 1 NOTE: Disable pull-up resistor Enable pull-up resistor P1.1 P1.2
A pull-up resistor of port 1 is automatically disabled when the corresponding pin is selected as push-pull output or alternative function.
Figure 10-3. Port 1 Pull-up Control Register (P1PUR)
10-2
S3CK318/FK318
I/O PORT
Port 1 Interrupt Edge Selection Register (P1EDGE) 26H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P1.0 Not used P1.3 P1EDGE configuration settings: 0 1 Falling edge interrupt Rising edge interrupt P1.1 P1.2
Figure 10-4. Port 1 Interrupt Edge Selection Register (P1EDGE)
10-3
I/O PORT
S3CK318/FK318
PORT 2
Port 2 Control Register (P2CON) 28H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P2.3/AD3
P2.2/AD2
P2.1/AD1
P2.0/AD0
P2CON bit-pair pin configuration settings: 0 0 1 1 0 1 0 1 Schmitt trigger input mode Output mode, open-drain Alternative function (AD0, AD1, AD2, AD3) Output mode, push-pull
Figure 10-5. Port 2 Control Register (P2CON)
Port 2 Pull-up Control Register (P2PUR) 29H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P2.0 Not used P2.3 P2 pull-up resistor settings: 0 1 NOTE: Disable pull-up resistor Enable pull-up resistor P2.1 P2.2
A pull-up resistor of port 2 is automatically disabled when the corresponding pin is selected as push-pull output or alternative function.
Figure 10-6. Port 2 Pull-up Control Register (P2PUR)
10-4
S3CK318/FK318
I/O PORT
PORT 3
Port 3 Control Register A (P3CONA) 2CH, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P3.1/INT5
P3.0/INT4/DAO
P3CONA bits pin configuration settings: 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Schmitt trigger input mode; pull-up; interrupt on falling edge Schmitt trigger input mode; interrupt on rising edge Schmitt trigger input mode; interrupt on rising or falling edge Output mode; push-pull Output mode; open-drain Alternative function (DAO)
Figure 10-7. Port 3 Control Register A (P3CONA)
Port 3 Control Register B (P3CONB) 2DH, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P3.3/SI/SEG1
P3.2/INT6/SEG0
P3CONB bits pin configuration settings: 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Schmitt trigger input mode; pull-up; interrupt on falling edge (SI) Schmitt trigger input mode; interrupt on rising edge (SI) Schmitt trigger input mode; interrupt on rising or falling edge (SI) Output mode; push-pull Output mode; open-drain Not available
Figure 10-8. Port 3 Control Register B (P3CONB)
10-5
I/O PORT
S3CK318/FK318
Port 3 Control Register C (P3CONC) 2EH, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P3.5/SCK/SEG3
P3.4/SO/SEG2
P3CONC bits pin configuration settings: 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Schmitt trigger input mode; pull-up (SCK) Schmitt trigger input mode (SCK) Not available Output mode; push-pull Output mode; open-drain Alternative function 1 (SO, SCK output: push-pull) Alternative function 2 (SO, SCK output: open-drain)
Figure 10-9. Port 3 Control Register C (P3CONC)
10-6
S3CK318/FK318
I/O PORT
PORT 4
Port 4 High-Byte Control Register (P4CONH) 30H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P4.7/SEG11 P4.6/SEG10
P4.5/SEG9
P4.4/SEG8
P4CONH bit-pair pin configuration settings: 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Output mode, open-drain Output mode, push-pull
Figure 10-10. Port 4 High-Byte Control Register (P4CONH)
Port 4 Low-Byte Control Register (P4CONL) 31H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P4.3/SEG7
P4.2/SEG6
P4.1/SEG5
P4.0/SEG4
P4CONL bit-pair pin configuration settings: 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Output mode, open-drain Output mode, push-pull
Figure 10-11. Port 4 Low-Byte Control Register (P4CONL)
10-7
I/O PORT
S3CK318/FK318
PORT 5
Port 5 High-Byte Control Register (P5CONH) 34H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P5.7/ SEG19/ COM4
P5.6/ SEG18/ COM5
P5.5/ SEG17/ COM6
P5.4/ SEG16/ COM7
P5CONH bit-pair pin configuration settings: 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Output mode, open-drain Output mode, push-pull
Figure 10-12. Port 5 High-Byte Control Register (P5CONH)
Port 5 Low-Byte Control Register (P5CONL) 35H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P5.3/ SEG15
P5.2/ SEG14
P5.1/ SEG13
P5.0/ SEG12
P5CONL bit-pair pin configuration settings: 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Output mode, open-drain Output mode, push-pull
Figure 10-13. Port 5 Low-Byte Control Register (P5CONL)
10-8
S3CK318/FK318
I/O PORT
PORT 6
Port 6 Control Register (P6CON) 36H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P6.3/ COM0
P6.2/ COM1
P6.1/ COM2
P6.0/ COM3
P6CON bit-pair pin configuration settings: 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Output mode, open-drain Output mode, push-pull
Figure 10-14. Port 6 Control Register (P6CON)
10-9
I/O PORT
S3CK318/FK318
NOTES
10-10
S3CK318/FK318
BASIC TIMER/WATCHDOG TIMER
11
OVERVIEW
* *
BASIC TIMER/WATCHDOG TIMER
WDTCON controls basic timer clock selection and watchdog timer clear bit. Basic timer is used in two different ways: As a clock source to watchdog timer to provide an automatic reset mechanism in the event of a system malfunction (When watchdog function is enabled in ROM code option) To signal the end of the required oscillation stabilization interval after a reset or stop mode release.
The reset value of basic timer clock selection bits is decided by the ROM code option. (see the section on ROM code option for details). After reset, programmer can select the basic timer input clock using WDTCON. When watchdog function is enabled by the ROM code option, programmer must set WDTCON.0 periodically within every 2048 x basic timer input clock time to prevent system reset.
Watchdog Timer Control Register (WDTCON) 0DH, R/W, Reset: X0H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
Not used
Watchdog timer clear bit: 0 1 Don't care Clear watchdog timer counter
Basic timer counter clock selection bits: 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fxx/2 fxx/4 fxx/16 fxx/32 fxx/128 fxx/256 fxx/1024 fxx/2048
Basic timer counter clear bit: 0 1 Don't care Clear basic timer counter
NOTE:
Under the reset operation, basic timer input clock source is effected by RCOD_OPT.14-.12. After reset, it can be selected basic timer clock source by writing appropriate value to WDTCON.6-.4.
Figure 11-1. Watchdog Timer Control Register (WDTCON)
11-1
BASIC TIMER/WATCHDOG TIMER
S3CK318/FK318
BLOCK DIAGRAM
Data Bus
RCOD_OPT .14, .13, .12
nRESET
MUX
WDTCON.6, .5, .4 nRESET, Stop or WDTCON.1 fxx/2048 fxx/1024 fxx/256 fxx/128 fxx/32 fxx/16 fxx/4 fxx/2 MUX fb Data Bus Clear 8-Bit Basic Timer Counter (Read Only) Bit 5 BT OVF BT INT IRQ0.5
(NOTE)
RCOD_OPT.11
3-Bit Watchdog Timer Counter Clear
OVF (System Reset)
WDTCON.0
nRESET
STOP
IDLE
NOTE:
CPU start signal (Bit 5 = 1/fb x 32) (Power down release)
Figure 11-2. Basic Timer & Watchdog Timer Functional Block Diagram
11-2
S3CK318/FK318
WATCH TIMER
12
OVERVIEW
Bit Name WTCON.7-.6 WTCON.5-.4
WATCH TIMER
The source of watch timer is fx/60 (main osc.) or fxt (sub osc.). The interval of watch timer interrupt can be selected by WTCON.3-2. Table 12-1. Watch Timer Control Register (WTCON): 8-Bit R/W Values - 0 0 1 1 WTCON.3-.2 0 0 1 1 WTCON.1 0 1 WTCON.0 0 1 0 1 0 1 0 1 0 1 Not used. 0.47 kHz buzzer (BUZ) signal output 0.94 kHz buzzer (BUZ) signal output 1.87 kHz buzzer (BUZ) signal output 3.75 kHz buzzer (BUZ) signal output Set watch timer interrupt to 1 sec. Set watch timer interrupt to 0.1 sec. Set watch timer interrupt to 0.5 sec. Set watch timer interrupt to 50 msec. Select fx/60 as the watch timer clock. Select fxt (sub osc) as the watch timer clock. Disable watch timer: clear frequency dividing circuits. Enable watch timer. Function Address 70H
NOTES: 1. The main clock frequency (fx) is assumed to be 4.5 MHz. 2. The watch timer clock frequency (fw) is assumed to be 75 kHz.
12-1
WATCH TIMER
S3CK318/FK318
WATCH TIMER CIRCUIT DIAGRAM
WTCON .4-.5
fw/160 (0.47 kHz) fw/80 (0.94 kHz) fw/40 (1.87 kHz) fw/20 (3.75 kHz) MUX Buzzer Output
50 msec fxt fx/60 Clock Selector fw Frequency Dividing Circuit 0.5 sec 0.1 sec 1 sec LCD Clock Selector Circuit Overflow WT INT IRQ1.0
WTCON .1
WTCON .0
WTCON .2-.3
fx = Main clock (4.5 MHz) fxt = Sub clock (75 kHz) fw = Watch timer clock
Figure 12-1. Watch Timer Circuit Diagram
12-2
S3CK318/FK318
16-BIT TIMER 0
13
OVERVIEW
16-BIT TIMER 0
The 16-bit timer 0 is an 16-bit general-purpose timer/counter. Timer 0 has three operating modes, one of which you select using the appropriate T0CON setting: -- Interval timer mode (Toggle output at T0OUT pin) -- Capture input mode with a rising or falling edge trigger at the T0CAP pin -- PWM mode (T0PWM) Timer 0 has the following functional components: -- Clock frequency divider (fxx divided by 4096, 512, 64, 8, or 1) with multiplexer -- External clock input pin (T0CLK) -- 16-bit counter (T0CNTH/L), 16-bit comparator, and 16-bit reference data register (T0DATAH/L) -- I/O pins for capture input (T0CAP), or PWM or match output (T0PWM, T0OUT) -- Timer 0 overflow interrupt (IRQ0.1) and match/capture interrupt (IRQ0.0) generation -- Timer 0 control register, T0CON (40H, read/write)
13-1
16-BIT TIMER 0
S3CK318/FK318
FUNCTION DESCRIPTION Timer 0 Interrupts (IRQ0.0, IRQ0.1) The timer 0 module can generate two interrupts, the timer 0 overflow interrupt (T0OVF), and the timer 0 match/capture interrupt (T0INT). T0OVF is interrupt level IRQ0.1. T0INT belongs to interrupt level IRQ0.0. Interval Timer Function In interval timer mode, a match signal is generated and T0OUT is toggled when the counter value is identical to the value written to the T0 reference data register, T0DATAH/L. The match signal generates a timer 0 match interrupt (T0INT) and clears the counter. If, for example, you write the value 0010H to T0DATAH/L and 04H to T0CON, the counter will increment until it reaches 0010H. At this point, the T0 interrupt request is generated, the counter value is reset, and counting resumes. Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter but can generate a match interrupt. The counter runs continuously, overflowing at FFFFH, and then repeat the incrementing from 0000H. Whenever an overflow is occurred, an overflow (OVF) interrupt can be generated. Although you can use the match or the overflow interrupt in PWM mode, interrupts are not typically used in PWMtype applications. Instead, the pulse at the T0PWM pin is held to Low level as long as the reference data value is less than or equal to () the counter value and then pulse is held to High level for as long as the data value is greater than (>) the counter value. One pulse width is equal to tCLK Capture Mode In capture mode, a signal edge that is detected at the T0CAP pin opens a gate and loads the current counter value into the T0 data register. You can select rising or falling edges to trigger this operation. Timer 0 also gives you capture input source, the signal edge at the T0CAP pin. You select the capture input by setting the value of the timer 0 capture input selection bit in the port 1 control register, P1CON, (24H). When P1CON.5-.4 is 00, the T0CAP input or normal input is selected .When P1CON.5-.4 is set to 11, normal output is selected. Both kinds of timer 0 interrupts can be used in capture mode, the timer 0 overflow interrupt is generated whenever a counter overflow occurs, the timer 0 match/capture interrupt is generated whenever the counter value is loaded into the T0 data register. By reading the captured data value in T0DATAH/L, and assuming a specific value for the timer 0 clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the T0CAP pin.
13-2
S3CK318/FK318
16-BIT TIMER 0
TIMER 0 CONTROL REGISTER (T0CON) You use the timer 0 control register, T0CON, to -- Select the timer 0 operating mode (interval timer, capture mode, or PWM mode) -- Select the timer 0 input clock frequency -- Clear the timer 0 counter, T0CNTH/L T0CON is located at address 40H, and is read/written addressable. A reset clears T0CON to '00H'. This sets timer 0 to normal interval timer mode, and selects an input clock frequency of fxx/4096. To disable the counter operation, please set T0CON.7-.5 to 111B. You can clear the timer 0 counter at any time during normal operation by writing a "1" to T0CON.2.
Timer 0 Control Register (T0CON) 40H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Timer 0 input clock selection bits: 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 fxx/4096 fxx/512 fxx/64 fxx/8 fxx/1 External clock (T0CLK) falling edge External clock (T0CLK) rising edge Counter stop 0 0 1 1 0 1 0 1
Not used Timer 0 counter clear bit: 0 1 No effect Clear the timer 0 counter (when write)
Timer 0 operating mode selection bits: Interval mode Capture mode (capture on rising edge, counter running, OVF can occur) Capture mode (capture on falling edge, counter running, OVF can occur) PWM mode (OVF & match interrupt can occur)
Figure 13-1. Timer 0 Control Register (T0CON)
13-3
16-BIT TIMER 0
S3CK318/FK318
BLOCK DIAGRAM
T0CON.7-5 Data Bus fXX/4096 fXX/512 fXX/64 fXX/8 fXX/1 T0CLK VSS M U X Timer 0 Buffer Reg 8 M U X 16-bit Comparator 16-bit Up-Counter (Read Only) R
OVF
T0OVF
IRQ0.1
T0CON.2 Clear
Match
M U X
T0INT
IRQ0.0
T0CAP
T0OUT T0PWM T0CON.4-.3
T0CON.4-.3
Counter Clear Signal or Match
Timer 0 Data H/L Register 8 Data Bus
Figure 13-2. Timer 0 Functional Block Diagram
13-4
S3CK318/FK318
16-BIT TIMER 0
Timer 0 Counter High-Byte Register (T0CNTH) 43H, Read only, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Timer 0 Counter Low-Byte Register (T0CNTL) 44H, Read only, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Timer 0 Data High-Byte Register (T0DATAH) 41H, R/W, Reset: FFH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Timer 0 Data Low-Byte Register (T1DATAL) 42H, R/W, Reset: FFH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Figure 13-3. Timer 0 Counter and Data Register (T0CNTH/L, T0DATAH/L)
13-5
16-BIT TIMER 0
S3CK318/FK318
NOTES
13-6
S3CK318/FK318
8-BIT TIMER 1
14
OVERVIEW
8-BIT TIMER 1
The 8-bit timer 1 is an 8-bit general-purpose timer. Timer 1 has the interval timer mode by using the appropriate T1CON setting. Timer 1 has the following functional components: -- Clock frequency divider (fxx divided by 1024, 256, 64, 8, or 1) with multiplexer -- 8-bit counter (T1CNT), 8-bit comparator, and 8-bit reference data register (T1DATA) -- Timer 1 interrupt (IRQ0.2) generation -- Timer 1 control register, T1CON (48H, read/write)
FUNCTION DESCRIPTION
Interval Timer Function The timer 1 module can generate an interrupt, the timer 1 match interrupt (T1INT). T1INT belongs to interrupt level IRQ0.2. In interval timer mode, a match signal is generated when the counter value is identical to the values written to the T1 reference data registers, T1DATA. The match signal generates a timer 1 match interrupt (T1INT) and clears the counter. If, for example, you write the value 10H to T1DATA and 0CH to T1CON, the counter will increment until it reaches 10H. At this point, the T1 interrupt request is generated, the counter value is reset, and counting resumes.
14-1
8-BIT TIMER 1
S3CK318/FK318
TIMER 1 CONTROL REGISTER (T1CON) You use the timer 1 control register, T1CON, to -- Enable the timer 1 operating (interval timer) -- Select the timer 1 input clock frequency -- Clear the timer 1 counter, T1CNT T1CON is located, at address 48H, and is read/written addressable. A reset clears T1CON to "00H". This sets timer 1 to disable interval timer mode, and selects an input clock frequency of fxx/1024. You can clear the timer 1 counter at any time during normal operation by writing a "1" to T1CON.3
Timer 1 Control Register (T1CON) 48H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Timer 1 input clock selection bits: 0 0 1 1 0 0 1 0 1 0 0 0 0 0 1 fxx/1024 fxx/256 fxx/64 fxx/8 fxx
Not used Timer 1 count enable bit:
Not used
0 Disable counting operation 1 Enable counting operation
Timer 1 counter clear bit: 0 No affect 1 Clear the timer 1 counter (when write)
NOTE: For normal operation T1CON.2 bit must be set 1.
Figure 14-1. Timer 1 Control Register (T1CON)
14-2
S3CK318/FK318
8-BIT TIMER 1
BLOCK DIAGRAM
Bits 7, 6, 5 Data Bus fxx/1024 fxx/256 fxx/64 fxx/8 fxx/1 X 8-bit Comparator Match Bit 2 Timer 1 Buffer Reg DA Converter T1INT IRQ0.2 M U 8 8-bit up-Counter (Read Only) Bit 3
R Clear
Counter clear (T1CON.3) signal or match signal
Timer 1 Data Reg (Read/Write)
8 Data Bus
NOTE:
T1CON.3 bit is cleared automatically.
Figure 14-2. Timer 1 Functional Block Diagram
14-3
8-BIT TIMER 1
S3CK318/FK318
Timer 1 Counter (T1CNT) 4AH, Read only, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Figure 14-3. Timer 1 Counter (T1CNT)
Timer 1 Data Register (T1DATA) 49H, R/W, Reset: FFH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Figure 14-4. Timer 1 Data Register (T1DATA)
14-4
S3CK318/FK318
SERIAL I/O INTERFACE
15
OVERVIEW
1. 2. 3.
SERIAL I/O INTERFACE
The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. To ensure flexible data transmission rates, you can select an internal or external clock source. PROGRAMMING PROCEDURE To program the SIO modules, follow these basic steps: Configure the I/O pins at port (SO, SCK, SI) by loading the appropriate value to the P3CONB and P3CONC registers, if necessary. Load an 8-bit value to the SIOCON register to properly configure the serial I/O module. In this operation, SIOCON.2 must be set to "1" to enable the data shifter. When you transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift operation starts.
15-1
SERIAL I/O INTERFACE
S3CK318/FK318
SIO CONTROL REGISTER (SIOCON)
Serial I/O Module Control Register (SIOCON) 58H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
SIO shift clock select bit: 0 Internal clock (P.S clock) 1 External clock (SCK) Data direction control bit: 0 1 MSB-first LSB-first SIO mode selction bit: 0 Rececive-only mode 1 Transmit/receive mode
Not used SIO shift operation enable bit: 0 Disable shifter and clock 1 Enable shfter and clock SIO counter clear and shift start bit: 0 No action 1 Clear 3-bit counter and start shifting
Shift clock edge selction bit: 0 Tx at falling edge, Rx at rising edge 1 Tx at rising edge, Rx at falling edge
Figure 15-1. Serial I/O Module Control Registers (SIOCON)
SIO PRE-SCALER REGISTER (SIOPS)
The value stored in the SIO pre-scaler registers, SIOPS, lets you determine the SIO clock rate (baud rate) as follows: Baud rate = Input clock( fxx/4)/(Pre-scaler value + 1), or, SCK input clock where fxx is a selected clock.
SIO Pre-scaler Register (SIOPS) 59H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Baud rate = (fxx /4)/(SIOPS + 1)
Figure 15-2. SIO Pre-scaler Register (SIOPS)
15-2
S3CK318/FK318
SERIAL I/O INTERFACE
BLOCK DIAGRAM
CLK
3-Bit Counter Clear SIOCON.3
IRQ0.4 (SIO INT)
SIOCON.7 (Shift Clock Source Select)
SIOCON.4 (Edge Select) SCK SIOPS fxx/2 8-Bit P.S 1/2 MUX
SIOCON.2 (Shift Enable)
SIOCON.5 (Mode Select) SO SIOCON.6 (LSB/MSB First Mode Select)
CLK 8-Bit SIO Shift Buffer (SIODATA)
8 SI
Data Bus
Figure 15-3. SIO Function Block Diagram
15-3
SERIAL I/O INTERFACE
S3CK318/FK318
SERIAL I/O TIMING DIAGRAM
SCK
SI
D17
D16
D15
D14
D13
D12
D11
D10
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
IRQS Set SIOCON.3
Transmit Complete
Figure 15-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)
SCK
SI
D17
D16
D15
D14
D13
D12
D11
D10
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
IRQS Set SIOCON.3
Transmit Complete
Figure 15-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)
15-4
S3CK318/FK318
BATTERY LEVEL DETECTOR
16
OVERVIEW
BATTERY LEVEL DETECTOR
The S3CK318/FK318 micro-controller has a built-in BLD (Battery Level Detector) circuit which allows detection of power voltage drop through software. Turning the BLD operation on and off can be controlled by software. Because the IC consumes a large amount of current during BLD operation. It is recommended that the BLD operation should be kept OFF unless it is necessary. Also the BLD criteria voltage can be set by the software. The criteria voltage can be set by matching to one of the 3 kinds of voltage. 2.2 V, 2.4 V or 2.6 V (VDD reference voltage) The BLD block works only when BLDCON.0 is set. If VDD level is lower than the reference voltage selected with BLDCON.4-.2, BLDCON.1 will be set. If VDD level is higher, BLDCON.1 will be cleared. When users need to minimize current consumption, do not operate the BLD block.
VDD Pin
fBLD
Battery Level Detector
BLDCON.1 BLD Out
BLDCON.0 Battery Level Setting BLD Run
BLDCON.4-.2 Set the Level
Figure 16-1. Block Diagram for Battery Level Detect
16-1
BATTERY LEVEL DETECTOR
S3CK318/FK318
BATTERY LEVEL DETECTOR CONTROL REGISTER (BLDCON) The bit 0 of BLDCON controls to run or disable the operation of battery level detect. Basically this VBLD is set as invalid by system reset and it can be changed in 3 kinds voltages by selecting Battery Level Detect Control register (BLDCON). When you write 3-bit data value to BLDCON, an established resistor string is selected and the VBLD is fixed in accordance with this resistor. Table 16-1 shows specific VBLD of 3 levels.
Resistor String MSB
Battery Level Detector Control Register (BLDCON) 71H, R/W, Reset: 00H .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
RVLD VIN Comparator BLD OUT VREF Bias BANDGAP
BLD Enable/Disable
NOTES: 1. The Reset value of BLDCON is #00H. 2. VREF is about 1 volt.
Figure 16-2. Battery Level Detector Circuit and Control Register
Table 16-1. BLDCON Value and Detection Level VLDCON .4-.2 100 101 110 111 VBLD 2.2 V 2.4 V 2.6 V -
16-2
S3CK318/FK318
LCD CONTROLLER/DRIVER
17
OVERVIEW
-- LCD controller/driver
LCD CONTROLLER/DRIVER
The S3CK318/FK318 microcontroller can directly drive an up-to-128-dot (16 segments x 8 commons) LCD panel. Its LCD block has the following components:
-- Display RAM for storing display data -- 4 common/segment output pins (COM4/SEG19-COM7/SEG16) -- 16 segment output pins (SEG0-SEG15) -- 4 common output pins (COM0-COM3) -- Internal resistor circuit for LCD bias To use the LCD controller/driver, the watch timer must be enabled by setting WTCON.0 to "1" because fLCD for LCD controller/driver clock source is supplied by the watch timer. When a sub block is selected as the watch timer clock source and watch timer is enabled, the LCD display can be enabled even during stop and idle modes. The LCD clock source speed, duty, bias LCD contrast level, and display on or off are determined by bit settings in the LCD control register, LMOD, at address 60H. Data written to the LCD display RAM can be transferred to the segment signal pins automatically without program control.
4 Data Bus LCD Controller/ Driver
COM0-COM3/P6.3-P6.0
8
4
COM4-COM7/SEG19-SEG16/P5.7-P5.4
16
SEG0-SEG15/P3.2-P5.3
Figure 17-1. LCD Function Diagram
17-1
LCD CONTROLLER/DRIVER
S3CK318/FK318
LCD CIRCUIT DIAGRAM
Port Latch
SEG0/P3.2 SEG/Port Driver SEG15/P5.3 SEG16/COM7/P5.4 SEG19/COM4/P5.7 COM0/P6.3
LCD Display RAM (180H-193H) fLCD
Data Bus
COM/Port Driver
COM3/P6.0 COM4/SEG19/P5.7 COM7/SEG16/P5.4
Timing Controller
LMOD
LCD Voltage Controller
Figure 17-2. LCD Circuit Diagram
17-2
S3CK318/FK318
LCD CONTROLLER/DRIVER
LCD RAM ADDRESS AREA RAM addresses of page 1 are used as LCD data memory. These locations can be addressed by 1-bit or 8-bit instructions. If the bit value of a display segment is "1", the LCD display is turned on. If the bit value is "0", the display is turned off. Display RAM data are sent out through the segment pins, SEG0-SEG19, using the direct memory access (DMA) method that is synchronized with the fLCD signal. RAM addresses in this location that are not used for LCD display can be allocated to general-purpose use.
1/8 Duty Mode COM COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 Bit .0 .1 .2 .3 .4 .5 .6 .7 SEG0 SEG1 SEG2 SEG3 -----SEG13 SEG14 SEG15
180H
181H
182H
183H
------
18DH
18EH
18FH
1/4, 1/3 Duty Mode COM COM0 COM1 COM2 COM3 Bit .0 .1 .2 .3 .4 .5 .6 .7 SEG0 SEG1 SEG2 SEG3 -----SEG17 SEG18 SEG19
180H
181H
182H
183H
------
191H
192H
193H
Figure 17-3. LCD Display Data RAM Organization
17-3
LCD CONTROLLER/DRIVER
S3CK318/FK318
LCD MODE CONTROL REGISTER (LMOD) The LCD mode control register for the LCD controller/driver is called LMOD. LMOD is located at address 60H. It has the following control functions: LCD duty selection LCD bias selection LCD clock selection LCD contrast level control LCD display control The LCD mode control register, LMOD is used to turn the LCD display on/off, to select duty and bias, to select LCD clock, and to select dividing resistors for bias. Following a reset all LMOD values are cleared to "0". This turns off the LCD display, select 1/3 bias and 1/3 duty, and select VDD for LCD panel power (V LCD). The LCD clock signal determines the frequency of COM signal scanning of each segment output. This is also referred as the frame frequency. Since the LCD clock signal is generated by the watch timer clock (fw), the watch timer must be enabled when the LCD display is turned on.
LCD Mode Control Register (LMOD) 60H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
LCD contrast level control bits (1/3 bias) 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 VLCD = VDD VLCD = 0.96 VDD VLCD = 0.92 VDD VLCD = 0.86 VDD VLCD = 0.80 VDD VLCD = 0.75 VDD VLCD = 0.70 VDD
LCD clock selection bits: (fw = 75 kHz) 0 0 1 1 0 1 0 1 234 Hz (fw/320) 469 Hz (fw/160) 938 Hz (fw/80) 1875 Hz (fw/40)
LCD duty and bias selection bits: 0 0 1 1 0 1 0 1 1/3 1/4 1/8 1/8 duty, duty, duty, duty, 1/3 1/3 1/4 1/5 bias; bias; bias; bias; COM0-COM2/SEG0-SEG19 COM0-COM3/SEG0-SEG19 COM0-COM7/SEG0-SEG15 COM0-COM7/SEG0-SEG15
LCD Display Control bit: 0 1 Display off (Cut off the LCD voltage dividing resistors) Normal display on
Figure 17-4. LCD Mode Control Register (LMOD)
17-4
S3CK318/FK318
LCD CONTROLLER/DRIVER
LCD PORT CONTROL REGISTERS (LPOT0, LPOT1, LPOT2)
LCD Port Control Register 0 (LPOT0) 61H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
SEG7/P4.3 SEG6/P4.2 SEG5/P4.1
SEG0/P3.2 SEG1/P3.3 SEG2/P3.4
SEG4/P4.0 SEG3/P3.5 LPOT0.n bit configuration settings: 0 1 NOTE: SEG Port Normal I/O Port "n" is 0, 1, 2, 3, 4, 5, 6, and 7.
Figure 17-5. LCD Port Control Register 0 (LPOT0)
LCD Port Control Register 1 (LPOT1) 62H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
SEG15/P5.3 SEG14/P5.2 SEG13/P5.1 SEG12/P5.0
SEG8/P4.4 SEG9/P4.5 SEG10/P4.6 SEG11/P4.7
LPOT1.n bit configuration settings: 0 1 NOTE: SEG Port Normal I/O Port "n" is 0, 1, 2, 3, 4, 5, 6, and 7.
Figure 17-6. LCD Port Control Register 1 (LPOT1)
17-5
LCD CONTROLLER/DRIVER
S3CK318/FK318
LCD Port Control Register 2 (LPOT2) 63H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
COM0/P6.3 COM1/P6.2 COM2/P6.1 COM3/P6.0
SEG16/COM7/P5.4 SEG17/COM6/P5.5 SEG18/COM5/P5.6 SEG19/COM4/P5.7
LPOT2.n bit configuration settings: 0 1 NOTE: SEG or COM Port Normal I/O Port "n" is 0, 1, 2, 3, 4, 5, 6, and 7.
Figure 17-7. LCD Port Control Register 2 (LPOT2)
17-6
S3CK318/FK318
LCD CONTROLLER/DRIVER
LCD VOLTAGE DIVIDING RESISTORS
1/5 Bias S3CK318 VDD
1/4 Bias S3CK318 VDD
1/3 Bias S3CK318 VDD
LMOD.4 Contrast Controller VLC1 VLC2 VLC3 VLC4 VLC5 VSS R R R R R
LMOD.4 Contrast Controller VLC1 VLC2 VLC3 VLC4 VLC5 VSS R R R R R
LMOD.4 Contrast Controller VLC1 VLC2 VLC3 VLC4 VLC5 VSS R R R R R
LMOD.5-.7
LMOD.5-.7
LMOD.5-.7
Figure 17-8. LCD Bias Circuit Connection
17-7
LCD CONTROLLER/DRIVER
S3CK318/FK318
COMMON (COM) SIGNALS The common signal output pin selection (COM pin selection) varies according to the selected duty cycle. -- In 1/3 duty mode, COM0-COM2 pins are selected. -- In 1/4 duty mode, COM0-COM3 pins are selected. -- In 1/8 duty mode, COM0-COM7 pins are selected. When 1/3 duty is selected by setting LMOD.3-LMOD.2 to "00", COM3-COM7 (P6.0, P5.7-P5.4) can be used for I/O ports, and when 1/4 duty is selected by setting LMOD.3-LMOD.2 to "01", COM4-COM7 (P5.7-P5.4) can be used for I/O ports.
SEGMENT (SEG) SIGNALS The 20 LCD segment signal pins are connected to corresponding display RAM locations at 80H-93H of page 1. Bits of the display RAM are synchronized with the common signal output pins. When the bit value of a display RAM location is "1", a 'select' signal (Display ON) is sent to the corresponding segment pin. When the display bit is "0", a 'non-select' signal (Display Off) is sent to the corresponding segment pin.
17-8
S3CK318/FK318
LCD CONTROLLER/DRIVER
SEG2 SEG1
SEG0 FR
0
1
2
0
1
2
VLC1 VSS
COM0
1 FRAME VLC1
COM1 COM2
COM0
VLC2(VLC3) VLC4(VLC5) VSS VLC1
COM1
VLC2(VLC3) VLC4(VLC5) VSS VLC1
COM2
VLC2(VLC3) VLC4(VLC5) VSS VLC1
SEG0
VLC2(VLC3) VLC4(VLC5) VSS
VLC1 SEG1 VLC2(VLC3) VLC4(VLC5) VSS + VLC1 + 1/3 VLC1 SEG0 - COM0 0V - 1/3 VLC1 -VLC1
Figure 17-9. LCD Signal Waveforms (1/3 Duty, 1/3 Bias)
17-9
LCD CONTROLLER/DRIVER
S3CK318/FK318
SEG1
SEG0 FR
0
1
2
3
0
1
2
3
VLC1 VSS
COM0 COM1 COM2 COM3 COM0
1 FRAME VLC1 VLC2 (VLC3) VLC4 (VLC5) VSS VLC1 COM1 VLC2 (VLC3) VLC4 (VLC5) VSS VLC1 COM2 VLC2 (VLC3) VLC4 (VLC5) VSS VLC1 COM3 VLC2 (VLC3) VLC4 (VLC5) VSS VLC1 SEG0 VLC2 (VLC3) VLC4 (VLC5) VSS VLC1 SEG1 VLC2 (VLC3) VLC4 (VLC5) VSS + VLC1 + 1/3 VLC1 SEG0 - COM0 0V -1/3 VLC1 - VLC1
Figure 17-10. LCD Signal Waveforms (1/4 Duty, 1/3 Bias)
17-10
S3CK318/FK318
LCD CONTROLLER/DRIVER
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 S E G 5 S E G 6 S E G 7 S E G 8 S E G 9
0 FR
1
2
34
5
6
7
0
1
2
3
4
56
7
VLC1 VSS
1 FRAME VLC1 VLC2 COM0 VLC3 (VLC4) VLC5 VSS VLC1 VLC2 COM1 VLC3 (VLC4) VLC5 VSS VLC1 VLC2 COM2 VLC3 (VLC4) VLC5 VSS VLC1 VLC2 SEG5 VLC3 (VLC4) VLC5 VSS VLC1 VLC2 VLC3 (VLC4) SEG5- COM0 VLC5 0V -VLC5 -VLC3 (-VLC4) -VLC2 -VLC1
Figure 17-11. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)
17-11
LCD CONTROLLER/DRIVER
S3CK318/FK318
0 FR
12
3
4
5
6
7
0
1
2
3
45
6
7
VLC1 VSS
1 FRAME VLC1 VLC2 SEG6 VLC3 (VLC4) VLC5 VSS
VLC1 VLC2 VLC3 (VLC4) SEG6 - COM0 VLC5 0V -VLC5 -VLC3 (-VLC4) -VLC2 -VLC1
Figure 17-11. LCD Signal Waveforms (1/8 Duty, 1/4 Bias) (Continued)
17-12
S3CK318/FK318
LCD CONTROLLER/DRIVER
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 S E G 5 S E G 6 S E G 7 S E G 8 S E G 9
0 FR
1
2
3
7
01
2
3
7
VLC1 VSS
1 FRAME VLC1 VLC2 COM0 VLC3 VLC4 VLC5 VSS VLC1 VLC2 COM1 VLC3 VLC4 VLC5 VSS VLC1 VLC2 COM2 VLC3 VLC4 VLC5 VSS VLC1 VLC2 SEG5 VLC3 VLC4 VLC5 VSS
Figure 17-12. LCD Signal Waveforms (1/8 Duty, 1/5 Bias)
17-13
LCD CONTROLLER/DRIVER
S3CK318/FK318
0 FR
1
2
3
7
0
12
3
7
VLC1 VSS
1 FRAME VLC1 VLC2 SEG6 VLC3 VLC4 VLC5 VSS
VLC1 VLC2 VLC3 VLC4 VLC5 SEG5 - COM0 0V - VLC5 - VLC4 - VLC3 - VLC2 - VLC1
VLC1 VLC2 VLC3 VLC4 VLC5 SEG6 - COM0 0V - VLC5 - VLC4 - VLC3 - VLC2 - VLC1
Figure 17-12. LCD Signal Waveforms (1/8 Duty, 1/5 Bias) (Continued)
17-14
S3CK318/FK318
10-BIT A/D CONVERTER
18
OVERVIEW
10-BIT ANALOG-TO-DIGITAL CONVERTER
The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 10-bit digital values. The analog input level must lie between the VDD and VSS values. The A/D converter has the following components: -- Analog comparator with successive approximation logic -- D/A converter logic (resistor string type) -- ADC control register (ADCON) -- Four multiplexed analog data input pins (AD0-AD3) -- 10-bit A/D conversion data output register (ADDATAH/ADDATAL) -- 4-bit digital input port (Alternately, I/O port)
FUNCTION DESCRIPTION
To initiate an analog-to-digital conversion procedure, at first you must set with alternative function for ADC input enable at port 2, the pin set with alternative function can be used for ADC analog input. And you write the channel selection data in the A/D converter control register ADCON.4-.5 to select one of the four analog input pins (AD0- AD3) and set the conversion start or disable bit, ADCON.0. The read-write ADCON register is located in address 5CH. The pins witch are not used for ADC can be used for normal I/O. During a normal conversion, ADC logic initially sets the successive approximation register to 800H (the approximate half-way point of an 10-bit register). This register is then updated automatically during each conversion step. The successive approximation block performs 10-bit conversions for one input channel at a time. You can dynamically select different channels by manipulating the channel selection bit value (ADCON.5-.4) in the ADCON register. To start the A/D conversion, you should set the enable bit, ADCON.0. When a conversion is completed, ADCON.3, the end-of-conversion (EOC) bit is automatically set to 1 and the result is dumped into the ADDATAH/ADDATAL register where it can be read. The A/D converter then enters an idle state. Remember to read the contents of ADDATAH/ADDATAL before another conversion starts. Otherwise, the previous result will be overwritten by the next conversion result. NOTE Because the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog level at the AD0-AD3 input pins during a conversion procedure be kept to an absolute minimum. Any change in the input level, perhaps due to noise, will invalidate the result. If the chip enters to STOP or IDLE mode in conversion process, there will be a leakage current path in A/D block. You must use STOP or IDLE mode after ADC operation is finished.
18-1
10-BIT A/D CONVERTER
S3CK318/FK318
CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for conversion clock with an 8 MHz fxx clock frequency, one clock cycle is 1 us. Each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 10-bit + set-up time = 50 clocks, 50 clock x 1 us = 50 us at 1 MHz (8 MHz/8) Note that A/D converter needs at least 25s for conversion time. A/D CONVERTER CONTROL REGISTER (ADCON) The A/D converter control register, ADCON, is located at address 5CH. It has three functions: -- Analog input pin selection (bits 5 and 4) -- End-of-conversion status detection (bit 3) -- ADC clock selection (bits 2 and 1) -- A/D operation start or disable (bit 0) After a reset, the start bit is turned off. You can select only one analog input channel at a time. Other analog input pins (AD0-AD3) can be selected dynamically by manipulating the ADCON.4-.5 bits. And the pins not used for analog input can be used for normal I/O function.
A/D Converter Control Register (ADCON) 5CH, R/W (EOC bit is read-only), Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Always logic zero A/D input pin selection bits: 0 0 1 1 0 1 0 1 AD0 AD1 AD2 AD3
Start or disable bit 0 1 Disable operation Start operation (This bit is cleared automatically after End-of-Conversion.)
Clock Selection bits: 0 0 1 1 End-of-conversion bit 0 1 Not complete Conversion Complete Conversion 0 1 0 1 fxx/8 fxx/4 fxx/2 fxx/1
Figure 18-1. A/D Converter Control Register (ADCON)
18-2
S3CK318/FK318
10-BIT A/D CONVERTER
A/D Converter Data Register (ADDATAH/ADDATAL) 5DH/5EH, Read Only MSB MSB .9 .1 .8 .0 .7 .6 .5 .4 .3 .2 LSB (ADDATAH) LSB (ADDATAL)
Figure 18-2. A/D Converter Data Register (ADDATAH/ADDATAL)
INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range AVSS to AVREF. Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. The reference voltage level for the first conversion bit is always 1/2 AVREF.
BLOCK DIAGRAM
ADCON.2-.1 ADCON.4-.5 (Select one input pin of the assigned pins)
Clock Selector
To ADCON.3 (EOC Flag)
ADCON.0 (AD/C Enable) M Input Pins AD0-AD3 (P2.0-P2.3) Analog Comparator Successive Approximation Logic & Register
. . .
U + X ADCON.0 (AD/C Enable)
P2CON (Assign Pins to ADC Input) 10-bit D/A Converter AVREF AVSS Conversion Result (ADDATAH/ADDATAL, 5DH/5EH)
Figure 18-3. A/D Converter Functional Block Diagram
18-3
10-BIT A/D CONVERTER
S3CK318/FK318
VDD Reference Voltage Input (AV REF = VDD) 10 F + C 103 VDD
VDD
Analog Input Pin C 101
AD0-AD3 S3CK318
VSS
Figure 18-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy
18-4
S3CK318/FK318
D/A CONVERTER
19
OVERVIEW
D/A CONVERTER
The 9-bit D/A Converter (DAC) module uses successive approximation logic to convert 9-bit digital values to 1 equivalent analog levels between VDD (1 - ) and VSS. 512 This D/A Converter consists of R-2R array structure. The D/A Converter has the following components: -- R-2R array structure -- Digital-to-analog converter control register (DACON) -- Digital-to-analog converter data register (DADATAH/DADATAL) -- Digital-to-analog converter output pin (DAO) FUNCTION DESCRIPTION To initiate a digital-to-analog conversion procedure, at first you must set with alternative function (P3CONA.2-.0) and set the digital-to-analog converter enable bit (DACON.0). The DACON register is located at the RAM address 74H. You should write the digital value calculated to digital-toanalog converter data register (DADATAH/DADATAL).
NOTE If the chip enters to power-down mode, STOP or IDLE, in conversion process, there will be current path in D/A Converter block. So. It is necessary to cut off the current path before the instruction execution enters power-down mode.
19-1
D/A CONVERTER
S3CK318/FK318
Data Bus
DADATA
.0
.1
.2
.3
.4
.5
.6
.7
.8
9-bit
DACON.1
Timer 1 Match Signal .8
DAC Buffer DACON.0
.0
.1
.2
.3
.4
.5
.6
.7
2R R 2R
2R R
2R
2R R
2R R
2R R
2R R
2R R
2R R DAO
Figure 19-1. DAC Circuit Diagram
D/A Converter Control Register (DACON) 74H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
Enable/Disable control bit: 0 Disable 1 Enable Data latch control bit: 0 1 The value of DADATA is always loaded into the DAC buffer. The value of DADATA is loaded into the DAC buffer when the timer 1 match is occurred.
Figure 19-2. Digital to Analog Converter Control Register (DACON)
19-2
S3CK318/FK318
D/A CONVERTER
D/A CONVERTER DATA REGISTER (DADATAH/DADATAL) The DAC DATA register, DADATAH/DADATAL is located at the RAM address, 75H-76H. DADATAH/DADATAL specifies the digital data to generate analog voltage. A reset initializes the DADATAH/DADATAL value to "00H". The D/A converter output value, VDAO, is calculated by the following formula.
n VDAO = VDD x 512
(n = 0-511, DADATAH/DADATAL value)
Table 19-1. DADATA Setting to Generate Analog Voltage
DADATAH.7 DADATAH.6 DADATAH.5 DADATAH.4 DADATAH.3 DADATAH.2 DADATAH.1 DADATAH.0 DADATAL.7 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 V DAO 0 V DD/21 V DD/22 V DD/23 V DD/24 V DD/25 V DD/26 V DD/27 V DD/28 V DD/29
NOTE:
These are the values determined by setting just one-bit of DADATA.0-DADATA.8. Other values of DAO can be obtained with superimposition.
D/A Converter Data Register (DADATAH/DADATAL) 75H/76H, R/W, Reset: 00H MSB MSB .8 .0 .7 .6 .5 .4 .3 .2 .1 LSB (DADATAH) LSB (DADATAL)
These bits should be always "0".
Figure 19-3. D/A Converter Data Register (DADATAH/DADATAL)
19-3
D/A CONVERTER
S3CK318/FK318
NOTES
19-4
S3CK318/FK318
FREQUENCY COUNTER
20
OVERVIEW
FREQUENCY COUNTER
The S3CK318 uses a frequency counter (FC) to counter the analog frequencies, FM, AM, SW, or digital pules. The FC block consists of a 1/16 divider, gate control circuit, FC control register (FCCON) and a 24-bit binary counter. The gate control circuit, which controls the frequency counting time, is programmed using the FCMOD register. Four different gate times can be selected using FCMOD register settings. During gate time, the 24-bit FC counts the input frequency at the FMF or AMF pins. The FMF or AMF pin input signal for the 24-bit counter is selected using FCCON register settings. When the FMF pin input signal is selected, the signal is divided by 16. When the AMF pin input signal is selected, the signal is directly connected or divided by 16 to the FC. P0.1/FMF and P0.0/AMF signals also can be used normal input port and count external events. By setting FCMOD register, the gate is opened for 16-ms, 32-ms or 64-ms periods. During the open period of the gate, input frequency is counted by the 24-bit counter. When the gate is closed, the counting operation is complete, and an interrupt is generated.
VDD P0.1 input P0PUR.1 FMF/P0.1 FCCON.2-.4 FCCON.2-.4 P0.0 input FCCON.1 FCCON.2-.4 P0PUR.0 AMF/P0.0 FCCON.2-.4 Vss FCMOD.2 FCMOD.0 -.1 FC start Gate Control Circuit Gate Signal Generator clear IRQ0.3 16/32/64 msec (fw =75 kHz) Sel 1/16 clear Sel Vss VDD FCNT2, 1, 0 24-bit Counter Data Bus
0.5 kHz Internal Signal
Figure 20-1. Frequency Counter Block Diagram
20-1
FREQUENCY COUNTER
S3CK318/FK318
FC CONTORL REGISTER (FCCON)
The FC control register (FCCON) is a 8-bit register that is used to stop/start frequency counting and select a signal of FMF or AMF.
Frequency Counter Control Register (FCCON) 78H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used 0 1 Frequency counter control bits: 0x0 0x1 100 101 110 111
Not used Frequency counter start bit: Stop increasing counter value Start increasing counter value
Select P0.1 signal (through the block dividing by 16), used to normal input or signal input. Select P0.0 signal, used to normal input or signal input. Select AMF signal; disable FMF pin (feedback resistor is off; pull-down through resistor), Input range is 0.5 - 5MHz. Select only FMF, 1/16-divided; disable AMF pin (feedback resistor is off; pull-down through resistor), Input range is 30 - 130 MHz. Select AMF signal, 1/16-divided; disable FMF pin (feedback resistor is off; pull-down through resistor), Input range is 5 - 30 MHz. Disable all inputs and frequency counter (feedback resistors are off, pull-down through resistors)
NOTES: 1. 'x' means 'don't care' 2. "FCCON.4" is a control bit which can be used to determine whether the P0.0 and P0.1 are of purpose with a frequency counter (analog input 300mVp-p) or general input port.
Figure 20-2. Frequency Counter Control Register (FCCON)
Frequency Counter Register (FCNT2 - FCNT0) 7CH - 7AH, R, Reset: 00H MSB .23 .22 .21 .20 .19 .18 .17 .16 LSB (FCNT2, 7CH)
MSB
.15
.14
.13
.12
.11
.10
.9
.8
LSB
(FCNT1, 7BH)
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
(FCNT0, 7AH)
Figure 20-3. Frequency Counter Register (FCNT2-FCNT0)
20-2
S3CK318/FK318
FREQUENCY COUNTER
Table 20-1. Frequency Counter Control Register (FCCON) Bit Settings in Normal Operating Mode FCCON.4 FCCON.3 FCCON.2 FMF's Feedback Resistor Off Off On Off Off AMF's Feedback Resistor Off On Off On Off FMF's Pull-down Off On Off On On AMF's Pull-down Off Off On Off On
0 1
x 0 0 1 1
x 0 1 0 1
Table 20-2. Frequency Counter Control Register (FCCON) Bit Settings in Power-Down Mode FCCON.4 FCCON.3 FCCON.2 FMF's Feedback Resistor Off Off AMF's Feedback Resistor Off Off FMF's Pull-down Off On AMF's Pull-down Off On
0 1
NOTE:
x x
x x
'x' means 'don't care'.
INPUT PIN CONFIGURATION FOR AN AC FREQUENCY COUNT Because the FMF and AMF pins have built-in AC amplifiers, DC component of the input signal must be stripped off by the external capacitor. When the FMF or AMF pin is selected for AC frequency counter function, the voltage level of the corresponding pin is increased to approximately 1/2 VDD after a sufficiently long time. If the pin voltage does not increase, the AC amplifier exceeds its operating range and maybe cause an FC malfunction. To prevent this from occurring, you should program a sufficiently long time delay interval before starting the count operation.
Capacitor IN S3CK318 Counter Input
Figure 20-4. FMF and AMF Pin Configuration
20-3
FREQUENCY COUNTER
S3CK318/FK318
FC MODE REGISTER (FCMOD)
FCMOD is a 8-bit register which can be used to select the gate time, and check whether a FC counting operation has been completed or not.
Frequency Counter Mode Register (FCMOD) 79H, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used FC gate state bit (Read only): 0 1
FC gate time selection bits: 0 0 1 1 0 1 0 1 Gate time is 16 ms Gate time is 32 ms Gate time is 64 ms Gate is open
This bit is cleared to "0", when FC counting is started by setting FCMOD.2 Gate is closed (After a specified gate time has elapsed) FC gate start bit: 0 1
Not affeced FC counting is started, gate state bit (FCMOD.7) and gate start bit (FCMOD.2) is cleared to "0" automatically . Clear frequency values (24-bit counter) and 1/16-divider.
Figure 20-5. Frequency Counter Mode Register (FCMOD)
20-4
S3CK318/FK318
FREQUENCY COUNTER
GATE TIMES
When you write a value to FCMOD, the FC gate is opened for a 16-millisecond, 32-millisecond, or 64-millisecond interval, setting with a rising clock edge. When the gate is open, the frequency at the AMF or FMF pin is counted by the 24-bit counter. When the gate closes, the FCMOD.7 is set to "1". An interrupt is then generated and the FC interrupt request bit (IRQ0.3) is set. Figure 20-6 shows gate timings with a 0.5 kHz internal clock.
Clock (0.5 kHz) Counting ends 16 ms Gate Time Counting ends 32 ms
64 ms Counting Period Gate open here FCCON, FCMOD is written; FC gate start bit (FCMOD.2) is set to 1 then FC gate state bit (FCMOD.7) is clear to 0 automatically Counting ends; FCMOD.7 bit is changed "1" and IRQ0.3 is set to "1".
Figure 20-6. Gate Timing (16, 32, or 64-ms)
20-5
FREQUENCY COUNTER
S3CK318/FK318
Selecting "Gate Remains Open" If you select "gate remain open" (FCMOD.0 and FCMOD.1 = '11'), the FC counts the input signal during the open period of the gate. The gate closes the next time a value is written to FCMOD.
Clock (0.5 kHz)
Gate Time Counting Period The gate closes when FCMOD is rewritten Gate is opened by writing FCMOD
Figure 20-7. Gate Timing (When Open) When you select "gate remains open" as the gating time, you can control the opening and closing of the gate in one of two ways: -- Set the gate time to a specific interval (16-ms, 32-ms, or 64-ms) by setting bits FCMOD.1 and FCMOD.0.
Gate Time
Set FCMOD.1 = FCMOD.0 = "1"
Set non-open gate time (16-, 32-, 64-ms) by bit FCMOD.1 and FCMOD.0
-- Disable FC operation by setting bits FCCON.4-.2 to "111b". This method lets the gate remain open, and stops the counting operation.
Gate Time
Set FCMOD.1 = FCMOD.0 = "1"
Set FCCON.4 = FCCON.3 = FCCON.2 = "1" FC counting operation is stopped.
20-6
S3CK318/FK318
FREQUENCY COUNTER
Gate Time Errors A gate time error occurs whenever the gate signals are not synchronized to the interval instruction clock. That is, the FC does not start counter operation until a rising edge of the gate signal is detected, even though the counter start instruction (setting bit FCMOD.2) has been executed. Therefore, there is a maximum 16-ms timing error (see Figure 20-8). After you have executed the FC start instruction, you can check the gate state at any time. Please note, however that the FC does not actually start its counting operation until stabilization time for the gate control signal has elapsed.
Instruction Execution (FCMOD Setting) 16 ms Clock (0.5 kHz)
Actual Gate Signal (16 ms)
Resulting Gate Signal
Gate Time Errors
Actual Counting Period
Figure 20-8. Gate Timing (16-ms Error) Counting Errors The frequency counter counts the rising edges of the input signal in order to determine the frequency. If the input signal is High level when the gate is open, one additional pulse is counted. When the gate is close, however, counting is not affected by the input signal status. In other words, the counting error is "+1, 0".
20-7
FREQUENCY COUNTER
S3CK318/FK318
FREQUENCY COUNTER (FC) OPERATION
FCCON register bits 4-2 are used to select the input pin and the register bit 1 is use to start or stop FC increasing a counter value. The counting operation of FC is started by setting FCMOD.2 to "1". You stop the counting operation by setting FCCON.4-.2 to "111b". The FCNT2-0 retains its previous value until FCCON and FCMOD register values are specified. Setting bit FCMOD.2 starts the frequency counting operation. Counting continues as long as the gate is open. The 24-bit counter value is automatically cleared to 000000H after it overflow (at FFFFFFH), and continues counting from zero. A reset operation clears the counter to zero. FCNT2 FCNT2.7 FCNT2.6 FCNT2.5 FCNT2.4 FCNT2.3 FCNT2.2 FCNT2.1 FCNT2.0
FCNT1
FCNT1.7
FCNT1.6
FCNT1.5
FCNT1.4
FCNT1.3
FCNT1.2
FCNT1.1
FCNT1.0
FCNT0
FCNT0.7
FCNT0.6
FCNT0.5
FCNT0.4
FCNT0.3
FCNT0.2
FCNT0.1
FCNT0.0
When the specified gate open time has elapsed, the gate closes in order to complete the counter operation. At this time, the FC counting ends interrupt request bit (IRQ0.3) is automatically set to "1" and an interrupt is generated. The corresponding IRQ bit must be cleared to "0" by software when the interrupt is serviced (Refer to chapter 6 to clear IRQ bit). The FCMOD.7 is set to "1" at the same time the gate is closed. Since the FCMOD.7 is cleaned to "0" when FC operation start, you can check the FCMOD.7 to determine when FC operation stops (that is, when the specified gate open time has elapsed). The frequency applied to FMF or AMF pin is counted while the gate is open. The relationship between the count value (N) and input frequencies fFMF and fAMF is shown below. FMF (divided by 16 before counting) pin input frequency is fFMF = N (DEC) x 16 TG
when TG = gate time (16 ms, 32 ms, 64 ms) AMF (divided by 16 before counting) pin input frequency is fAMF = N (DEC) x 16 TG
when TG = gate time (16 ms, 32 ms, 64 ms) AMF pin input frequency is fAMF = N (DEC) TG
when TG = gate time (16 ms, 32 ms, 64 ms)
20-8
S3CK318/FK318
FREQUENCY COUNTER
Table 20-3 shows the range of frequency that you can apply to the AMF and FMF pins. Table 20-3. FC Frequency Characteristics Pin AMF AMF (divided by 16) FMF (divided by 16) Voltage Level 300 m VPP (min) 300 m VPP (min) 300 m VPP (min) Frequency Range 0.5 MHz to 5 MHz 5 MHz to 30 MHz 30 MHz to 130 MHz
FC DATA CALCULATION
Selecting the FMF pin for FC Input First, divide the signal at the FMF pin by 16, and then apply this value to the frequency counter. This means that the frequency counter value is equal to one-sixteenth of the input signal frequency. FMF input frequency (fFMF): 80 MHz Gate time (TG): 32 ms FC counter value (N): N = (fFMF/16) x TG = 80 x 106/16 x 32 x 10-3 = 160000 = 027100H Bin Hex FCNT 0 0 0 FCNT2 0 0 0 0 2 1 0 0 1 7 FCNT1 1 1 0 0 1 0 1 0 0 0 FCNT0 0 0 0 0 0 0 0
20-9
FREQUENCY COUNTER
S3CK318/FK318
Selecting the AMF (divided by 16) Pin for FC Input First, divided the signal at the AMF pin 16, and then apply this value to the frequency counter. This means that the frequency counter value is equal to one-sixteenth of the input signal frequency. AMF input frequency (fAMF): 20 MHz Gate time (TG): 16 ms FC counter value (N): N = (fAMF/16) x TG = 20 x 106/16 x 16 x 10-3 = 20000 = 004E20H Bin Hex FCNT 0 0 0 FCNT2 0 0 0 0 0 0 0 0 1 4 FCNT1 0 0 1 1 E 1 0 0 0 2 FCNT0 1 0 0 0 0 0 0
Selecting the AMF Pin for FC Input The signal at AMF pin is directly input to the frequency counter. AMF input frequency (fAMF): 450 kHz Gate time (TG): 64 ms FC counter value (N): N = (fAMF) x TG = 450 x 103 x 64 x 10-3 = 28800 = 007080H Bin Hex FCNT 0 0 0 FCNT2 0 0 0 0 0 0 0 0 1 7 FCNT1 1 1 0 0 0 0 0 1 0 8 FCNT0 0 0 0 0 0 0 0
20-10
S3CK318/FK318
ELECTRICAL DATA
21
(TA = 25 C) Parameter Supply voltage Input voltage Output voltage Output current high
ELECTRICAL DATA
Table 21-1. Absolute Maximum Ratings
Symbol VDD VI VO IOH IOL TA TSTG
Conditions - - - One I/O pin active All I/O pins active
Rating - 0.3 to + 4.6 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 18 - 60 + 30 + 100 - 25 to + 85 - 65 to + 150
Unit V V V mA
Output current low
One I/O pin active Total pin current for port
mA
C C
Operating temperature Storage temperature
- -
Table 21-2. D.C. Electrical Characteristics (TA = - 25 C to + 85 C, VDD = 1.95 V to 3.6 V) Parameter Operating voltage Symbol VDD VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Output high voltage VOH VOL fx = 8 MHz fx = 2 MHz Input high voltage All input pins except VIH2, VIH3 P1, P2, P3, and nRESET XIN, XTIN All input pins except VIL2, VIL3 P1, P2, P3, and nRESET XIN, XTIN VDD = 2.7 V to 3.6 V; IOH = -1 mA, all output pins Output low voltage VDD = 2.7 V to 3.6 V; IOL = 8 mA, all output pins - - 1.0 VDD-1.0 - Conditions Min 2.3 1.95 0.7V DD 0.8V DD VDD-0.1 - - 0.3V DD 0.2V DD 0.1 - V V Typ - - - Max 3.6 3.6 VDD V Unit V
21-1
ELECTRICAL DATA
S3CK318/FK318
Table 21-2. D.C. Electrical Characteristics (Continued) (TA = - 25 C to + 85 C, VDD = 1.95 V to 3.6 V) Parameter Input high leakage current Symbol ILIH1 ILIH2 Input low leakage current ILIL1 ILIL2 Output high leakage current Output low leakage current Oscillator feedback resistors ILOH ILOL ROSC1 Conditions VIN = VDD All input pins except ILIH2 VIN = VDD ; XIN, XTIN VIN = 0 V All input pins except ILIL2 VIN = 0 V; XIN, XTIN, nRESET VOUT = VDD All I/O pins and output pins VOUT = 0 V All I/O pins and output pins VDD = 3.0 V, TA = 25 C XIN = VDD, XOUT = 0 V VDD = 3.0 V, TA = 25 C XTIN = VDD, XTOUT = 0 V VIN = 0 V; VDD = 3 V 10% Port 0,1,2,3,4,5,6 TA = 25 C VIN = 0 V; VDD = 3 V 10% TA = 25 C, nRESET only TA = 25 C - VDD = 2.7 V to 3.6 V LCD clock = 0 Hz TA = 25 C 600 1700 3000 k - - - - -20 3 -3 uA Min - Typ - Max 3 Unit uA
- -
- -
20 -3
ROSC2
3000
6000
9000
Pull-up resistor
RL1
40
70
140
RL2
200
400
800
LCD voltage dividing resistor LCD driving voltage (resistor bias) Middle output voltage
RLCD VLCD VLC1 VLC2 VLC3 VLC4 VLC5
40 2.5 VDD-0.2 0.8V DD-0.2 0.6V DD-0.2 0.4V DD-0.2 0.2V DD-0.2
55 - VDD 0.8V DD 0.6V DD 0.4V DD 0.2V DD
90 3.6 VDD+0.2 0.8V DD+ 0.2 0.6V DD+ 0.2 0.4V DD+ 0.2 0.2V DD+ 0.2 V V
21-2
S3CK318/FK318
ELECTRICAL DATA
Table 21-2. D.C. Electrical Characteristics (Concluded) (TA = - 25 C to + 85 C, VDD = 1.95 V to 3.6 V) Parameter COM output voltage deviation Symbol VDC Conditions VDD = VLC2 = 3 V (V LCD-COMi) Io = 15 A , (i = 0-7) SEG output voltage deviation VDS VDD = VLC2 = 3 V (V LCD-SEGi) Io = 15 A , (i = 0-19) Supply current
(1)
Min -
Typ 60
Max 120
Unit mV
-
60
120
IDD1 (2)
Main operating: FC enable VDD = 3 V 10 % 4.5 MHz crystal oscillator Main operating: VDD = 3 V 10 % 4.5 MHz crystal oscillator Idle mode: VDD = 3 V 10 % 4.5 MHz crystal oscillator Sub operating: main-osc stop VDD = 3 V 10 % 75 kHz crystal oscillator Sub idle mode: main-osc stop VDD = 3 V 10 % 75 kHz crystal oscillator Main stop mode : sub-osc stop VDD = 3 V 10 %, TA = 25 C
-
2.5
5
mA
IDD2 (2)
2
4
IDD3 (2) IDD4 (3)
- -
0.3 40
1.0 80 uA
IDD5 (3)
-
10
20
IDD6 (4)
-
0.2
2
NOTES: 1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, voltage level detector, ADC, DAC, FC or external output current loads. 2. IDD1, IDD2, and IDD3 includes a power consumption of sub oscillator. 3. 4. 5. IDD4 and IDD5 are the current when the main clock oscillation stop and the sub clock is used. IDD6 is the current when the main and sub clock oscillation stop. Every value in this table is measured when bits 2-0 of the power control register (PCON.2-.0) is set to 111B.
21-3
ELECTRICAL DATA
S3CK318/FK318
Table 21-3. A.C. Electrical Characteristics (TA = - 25 C to + 85 C, VDD = 1.95 V to 3.6 V) Parameter Interrupt input high, low width nRESET input low width Symbol tINTH, tINTL tRSL Conditions P1.0-P1.3, P3.0-P3.2 VDD = 3 V VDD = 3 V 10 % Min - Typ 200 Max - Unit ns s
10
-
-
tINTL
tINTH
0.8 VDD 0.2 VDD
Figure 21-1. Input Timing for External Interrupts (P1, P3.0-P3.2)
tRSL
nRESET 0.2 VDD
Figure 21-2. Input Timing for RESET
21-4
S3CK318/FK318
ELECTRICAL DATA
Table 21-4. Input/Output Capacitance (TA = -25 C to + 85 C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are returned to VSS. Min - Typ - Max 10 Unit pF
Table 21-5. Data Retention Supply Voltage in Stop Mode (TA = -25 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR VDDDR = 1.95 V Conditions - Min 1.95 - Typ - - Max 3.6 2 Unit V uA
Stop Mode Data Retention Mode VDD Execution of STOP Instruction nRESET 0.2VDD VDDDR
RESET Occur Oscillation Stabilization Time Normal Operating Mode
tWAIT
NOTE:
tWAIT is same as 2048 x 32 x 1/fxx when RCOD-OPT .14-.12 = "111b". That is, tWAIT is decided by RCOD-OPT .14-.12 when system Reset is generated.
Figure 21-3. Stop Mode Release Timing When Initiated by a RESET
21-5
ELECTRICAL DATA
S3CK318/FK318
OSC Start up time Stop Mode Data Retention VDD Execution of STOP Instruction INT 0.2 VDD VDDDR
Oscillation Stabilization Time
Normal Operating Mode
tWAIT
NOTE:
tWAIT is decided by WDTCON register setting. When bit 6, 5, 4 of WDTCON is "110"b, tWAIT is 1024 x 32 x 1/fxx.
Figure 21-4. Stop Mode (Main) Release Timing Initiated by Interrupts
Oscillation OSC Start Stabilization Time up time Stop Mode Data Retention VDD VDDDR Normal Operating Mode
Execution of STOP Instruction INT
0.2 VDD tWAIT NOTE: tWAIT is same as 256 x 32 x 1/fxx. The oscillator strat up time is less than 100 ms. The value of 256 which is selected for the clock source of basic timer must be kept within this value.
Figure 21-5. Stop Mode (Sub) Release Timing Initiated by Interrupts
21-6
S3CK318/FK318
ELECTRICAL DATA
Table 21-6. A/D Converter Electrical Characteristics (TA = - 25 C to 85 C, VDD = 2.0 V to 3.6 V) Parameter Resolution Total Accuracy Integral Linearity Error Differential Linearity Error Offset Error of Top Offset Error of Bottom Conversion Time (1) Analog Input Voltage Analog Input Impedance Analog Input Current Analog Block Current (2) ILE DLE EOT EOB TCON VIAN RAN IADIN IADC VDD = 3 V VDD = 3 V VDD = 3 V When power down mode
NOTES: 1. 'Conversion time' is the period between start and end of conversion operation. 2. IADC is an operating current during A/D conversion.
Symbol
Conditions
Min -
Typ 10 - - - 1 0.5
Max - 3 2 1 3 2 - VDD - 10 1.5 500
Unit bit LSB
VDD = 3.072 V VSS = 0 V fxx = 8MHz
-
10-bit resolution 50 x fxx/4, fxx = 8MHz - -
25 VSS 2 - -
- - - - 0.5 100
s V M A mA nA
Table 21-7. D/A Converter Electrical Characteristics (TA = - 25 C to 85 C, VDD = 2.0 V to 3.6 V, VSS = 0 V) Parameter Resolution Absolute Accuracy Differential Linearity Error Setup Time Output Resistance Symbol - - DLE tSU RO Conditions VDD = 3.072 V Min - -3 -2 - 6 Typ - - - - 9 Max 9 3 2 5 12 Unit bit LSB LSB s k
21-7
ELECTRICAL DATA
S3CK318/FK318
Table 21-8. Characteristics of Frequency Counter (TA = - 25 C to + 85 C, VDD = 2.0 V to 3.6 V) Parameter Input voltage (peak to peak) Frequency Symbol VIN fAMF Conditions AMF/FMF mode, sine wave input AMF mode, sine wave input; VIN = 300mVP-P FCCON.4-.2 = 100b AMF mode, sine wave input; VIN = 300mVP-P FCCON.4-.2 = 110b fFMF FMF mode, sine wave input; VIN = 300mVP-P FCCON.4-.2 = 101b 30 130 5 30 Min 0.3 0.5 Typ - - Max VDD 5 Units V MHz
Table 21-9. Characteristics of Battery Level Detect Circuit (TA = 25 C) Parameter Operating voltage of BLD Voltage of BLD Symbol VDDBLD VBLD BLDCON.4-.2 = 100b BLDCON.4-.2 = 101b BLDCON.4-.2 = 110b Current consumption IBLD BLD on VDD = 3.0 V VDD = 2.0 V Hysteresys voltage of BLD BLD circuit response time V TB BLDCON.4-.2 = 100b, 101b, 110b fw = 75 kHz - - Conditions Min 1.95 1.95 2.15 2.3 - Typ - 2.2 2.4 2.6 60 40 10 - Max 3.6 2.45 2.65 2.9 100 80 100 1 mV ms A Unit V
21-8
S3CK318/FK318
ELECTRICAL DATA
Table 21-10. LCD Contrast Level Characteristics (TA = - 25 C to 85 C, VDD = 2.5 V to 3.6 V) Parameter LCD drive voltage Symbol VLC1 Conditions Connect a 1Mohm load resistor between VSS and VLC1 (No panel load) LMOD Value 000 001 010 011 100 101 110 Min Typ. x 0.9 Typ VDD 0.96 VDD 0.92 VDD 0.86 VDD 0.80 VDD 0.75 VDD 0.70 VDD Max Typ. x 1.1 Unit V
21-9
ELECTRICAL DATA
S3CK318/FK318
Table 21-11. Synchronous SIO Electrical Characteristics (TA = - 25 C to + 85 C, VDD = 1.95 V to 3.6 V, VSS = 0 V, fxx = 8 MHz oscillator) Parameter SCK Cycle time Serial Clock High Width Serial Clock Low Width Serial Output data delay time Serial Input data setup time Serial Input data Hold time Symbol TCYC TSCKH TSCKL TOD TID TIH Conditions - - - - - - Min 250 75 75 - 50 125 Typ - - - - - - Max - - - 65 - - Unit ns
tCYC tSCKL SCK 0.8 VDD 0.2 VDD tID tIH 0.8 VDD SI Input Data 0.2 VDD tSCKH
tOD SO Output Data
Figure 21-6. Serial Data Transfer Timing
21-10
S3CK318/FK318
ELECTRICAL DATA
Table 21-12. Main Oscillator Frequency (fOSC1) (TA = - 25 C to + 85 C VDD = 1.95 V to 3.6 V) Oscillator Crystal/Ceramic Clock Circuit
XIN XOUT
Test Condition VDD = 1.95 V - 3.6 V
Min 0.4
Typ -
Max 2.0
Unit MHz
C1
C2
VDD = 2.3 V - 3.6 V External clock
XIN XOUT
8.0 0.4 - 2.0 MHz
VDD = 1.95 V - 3.6 V
VDD = 2.3 V - 3.6 V RC
XIN XOUT
8.0 0.4 - 1 MHz
VDD = 3 V
NOTE:
Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
Table 21-13. Main Oscillator Clock Stabilization Time (TST1) (TA = - 25 C to + 85 C, VDD = 1.95 V to 3.6 V) Oscillator Crystal Ceramic External clock
NOTE:
Test Condition VDD = 1.95 V to 3.6 V VDD = 1.95 V to 3.6 V XIN input high and low level width (t XH, tXL)
Min - - 62.5
Typ - - -
Max 30 10 1250
Unit ms ms ns
Oscillation stabilization time (TST1) is the time required for the CPU clock to return to its normal oscillation frequency after a power-on occurs, or when Stop mode is ended by a nRESET signal.
21-11
ELECTRICAL DATA
S3CK318/FK318
1/fosc1 tXL XIN tXH VDD - 0.1 V 0.1 V
Figure 21-7. Clock Timing Measurement at XIN
Table 21-14. Sub Oscillator Frequency (fOSC2) (TA = - 25 C to + 85 C, VDD = 1.95 V to 3.6 V) Oscillator Crystal Clock Circuit
XTIN XT OUT
Test Condition -
Min 32
Typ -
Max 100
Unit kHz
C1
C2
External clock
XTIN XT OUT
-
32
-
100
kHz
NOTE:
Oscillation frequency and Xtin input frequency data are for oscillator characteristics only.
1/fosc2 tXTL XT IN tXTH VDD - 0.1 V 0.1 V
Figure 21-8. Clock Timing Measurement at XTIN
21-12
S3CK318/FK318
ELECTRICAL DATA
Table 21-15. Sub Oscillator (Crystal) Start up Time (tST2) (TA = - 25 C to + 85 C, VDD = 1.95 V to 3.6 V) Oscillator Normal drive External clock
NOTE:
Test Condition VDD = 1.95 V to 3.6 V XTIN input high and low level width (t XTH, tXTL)
Min - 5
Typ - -
Max 10 15
Unit sec us
Oscillator stabilization time (tST2) is the time required for the oscillator to it's normal oscillation when stop mode is released by interrupts.
CPU CLOCK 8 MHz 4 MHz 2 MHz
0.4 MHz 1.95 V 2.3 V Supply Voltage (V) Minimum instruction clock = oscillator frequency 3.6 V
Figure 21-9. Operating Voltage Range
21-13
ELECTRICAL DATA
S3CK318/FK318
NOTES
21-14
S3CK318/FK318
MECHANICAL DATA
22
OVERVIEW
MECHANICAL DATA
The S3CK318/FK318 is available in 44-QFP-1010B package.
13.20
+ 0.30
0-8 10.00
+ 0.10
0.15 - 0.05
13.20 + 0.30
10.00
44-QFP-1010B
0.10 MAX
#44
#1 0.80
+ 0.10
0.35 - 0.05 0.15 MAX (1.00)
0.05 MIN 2.05 + 0.10 2.30 MAX
NOTE : Dimensions are in millimeters.
Figure 22-1. 44-Pin QFP Package Dimensions (44-QFP-1010B)
0.80 + 0.20
22-1
MECHANICAL DATA
S3CK318/FK318
NOTES
22-2
S3CK SERIES MASK ROM ORDER FORM
Product description: Device Number: S3CK__________- ___________ (write down the ROM code number) Product Order Form: Package Pellet Wafer Package Type: __________
Package Marking (Check One): Standard Custom A (Max 10 chars) Custom B (Max 10 chars each line)
SEC
@ YWW Device Name
@ YWW Device Name
@ YWW
@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly
Delivery Dates and Quantities: Deliverable ROM code Customer sample Risk order Please answer the following questions: See Risk Order Sheet Required Delivery Date - Quantity Not applicable Comments See ROM Selection Form
F
For what kind of product will you be using this order? New product Replacement of an existing product Upgrade of an existing product Other
If you are replacing an existing product, please indicate the former product name ( )
F
What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price Development system Used same micom before Product quality Technical support Quality of documentation Features and functions Delivery on time Samsung reputation
Mask Charge (US$ / Won): Customer Information: Company Name: Signatures:
____________________________
___________________ ________________________
Telephone number
_________________________
__________________________________
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
(Person placing the order)
(Technical Manager)
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
S3CK SERIES REQUEST FOR PRODUCTION AT CUSTOMER RISK
Customer Information: Company Name: Department: Telephone Number: Date: Risk Order Information: Device Number: Package: Intended Application: Product Model Number: S3CK________- ________ (write down the ROM code number) Number of Pins: ____________ Package Type: _____________________ ________________________________________________________________ ________________________________________________________________ __________________________ __________________________ Fax: _____________________________
________________________________________________________________ ________________________________________________________________
Customer Risk Order Agreement: We hereby request SEC to produce the above named product in the quantity stated below. We believe our risk order product to be in full compliance with all SEC production specifications and, to this extent, agree to assume responsibility for any and all production risks involved.
Order Quantity and Delivery Schedule: Risk Order Quantity: Delivery Schedule: Delivery Date (s) Quantity Comments _____________________ PCS
Signatures:
_______________________________ (Person Placing the Risk Order)
_______________________________________ (SEC Sales Representative)
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
S3FK SERIES FLASH FACTORY WRITING ORDER FORM
Product Description: Device Number: S3FK________-________ (write down the ROM code number) Package Pellet Package Type: Wafer _____________________
Product Order Form: If the product order form is package: Package Marking (Check One): Standard
Custom A (Max 10 chars)
Custom B (Max 10 chars each line)
SEC
@ YWW Device Name
@ YWW Device Name
@ YWW
@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly
Delivery Dates and Quantity: ROM Code Release Date Required Delivery Date of Device Quantity
Please answer the following questions:
F
What is the purpose of this order? New product development Replacement of an existing microcontroller Upgrade of an existing product Other
If you are replacing an existing microcontroller, please indicate the former microcontroller name ( )
F
What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price Development system Used same micom before Product quality Technical support Quality of documentation Features and functions Delivery on time Samsung reputation
Customer Information: Company Name: Signatures: ___________________ ________________________ Telephone number _________________________
__________________________________
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
(Person placing the order)
(Technical Manager)
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)

▲Up To Search▲

Price & Availability of S3FK318

	To Download S3FK318 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .